Datasheet

Peripheral Memory-Mapped Registers

56F8036 Data Sheet, Rev. 6

Freescale Semiconductor 49

Table 4-14 Power Supervisor Registers Address Map

(PS_BASE = $00 F140)

PS_CTRL $0 Control Register

PS_STAT $1 Status Register

Reserved

Table 4-15 GPIOA Registers Address Map

(GPIOA_BASE = $00 F150)

Address Offset Register Description

GPIOA_PUPEN $0 Pull-up Enable Register

GPIOA_DATA $1 Data Register

GPIOA_DDIR $2 Data Direction Register

GPIOA_PEREN $3 Peripheral Enable Register

GPIOA_IASSRT $4 Interrupt Assert Register

GPIOA_IEN $5 Interrupt Enable Register

GPIOA_IEPOL $6 Interrupt Edge Polarity Register

GPIOA_IPEND $7 Interrupt Pending Register

GPIOA_IEDGE $8 Interrupt Edge-Sensitive Register

GPIOA_PPOUTM $9 Push-Pull Output Mode Control Register

GPIOA_RDATA $A Raw Data Input Register

GPIOA_DRIVE $B Output Drive Strength Control Register

Table 4-16 GPIOB Registers Address Map

(GPIOB_BASE = $00 F160)

GPIOB_PUPEN $0 Pull-up Enable Register

GPIOB_DATA $1 Data Register

GPIOB_DDIR $2 Data Direction Register

GPIOB_PEREN $3 Peripheral Enable Register

GPIOB_IASSRT $4 Interrupt Assert Register

GPIOB_IEN $5 Interrupt Enable Register

GPIOB_IEPOL $6 Interrupt Edge Polarity Register

GPIOB_IPEND $7 Interrupt Pending Register

GPIOB_IEDGE $8 Interrupt Edge-Sensitive Register

GPIOB_PPOUTM $9 Push-Pull Output Mode Control Register

GPIOB_RDATA $A Raw Data Input Register

GPIOB_DRIVE $B Output Drive Strength Control Register