Datasheet

Peripheral Memory-Mapped Registers

56F8036 Data Sheet, Rev. 6

Freescale Semiconductor 51

Table 4-20 Programmable Interval Timer 1 Registers Address Map

(PIT1_BASE = $00 F1A0)

PIT1_CTRL $0 Control Register

PIT1_MOD $1 Modulo Register

PIT1_CNTR $2 Counter Register

Table 4-21 Programmable Interval Timer 2 Registers Address Map

(PIT2_BASE = $00 F1B0)

PIT2_CTRL $0 Control Register

PIT2_MOD $1 Modulo Register

PIT2_CNTR $2 Counter Register

Table 4-22 Digital-to-Analog Converter 0 Registers Address Map

(DAC0_BASE = $00 F1C0)

DAC0_CTRL $0 Control Register

DAC0_DATA $1 Data Register

DAC0_STEP $2 Step Register

DAC0_MINVAL $3 Minimum Value Register

DAC0_MAXVAL $4 Maximum Value Register

Table 4-23 Digital-to-Analog Converter 0 Registers Address Map

(DAC1_BASE = $00 F1D0)

DAC1_CTRL $0 Control Register

DAC1_DATA $1 Data Register

DAC1_STEP $2 Step Register

DAC1_MINVAL $3 Minimum Value Register

DAC1_MAXVAL $4 Maximum Value Register