Datasheet

56F8036 Data Sheet, Rev. 6

56 Freescale Semiconductor

Part 5 Interrupt Controller (ITCN)

5.1 Introduction

The Interrupt Controller (ITCN) module arbitrates between various interrupt requests (IRQs), signals to

the 56800E core when an interrupt of sufficient priority exists, and to what address to jump in order to

service this interrupt.

5.2 Features

The ITCN module design includes these distinctive features:

• Programmable priority levels for each IRQ

• Two programmable Fast Interrupts

• Notification to SIM module to restart clocks out of Wait and Stop modes

• Ability to drive initial address on the address bus after reset

For further information, see Table 4-2, Interrupt Vector Table Contents.

5.3 Functional Description

The Interrupt Controller is a slave on the IPBus. It contains registers that allow each of the 64 interrupt

sources to be set to one of four priority levels (excluding certain interrupts that are of fixed priority). Next,

all of the interrupt requests of a given level are priority encoded to determine the lowest numerical value

of the active interrupt requests for that level. Within a given priority level, number 0 is the highest priority

and number 63 is the lowest.

MSCAN_TXFG3 $33 Foreground Transmit Buffer 3

MSCAN_TXFG4 $34 Foreground Transmit Buffer 4

MSCAN_TXFG5 $35 Foreground Transmit Buffer 5

MSCAN_TXFG6 $36 Foreground Transmit Buffer 6

MSCAN_TXFG7 $37 Foreground Transmit Buffer 7

MSCAN_TXFG8 $38 Foreground Transmit Buffer 8

MSCAN_TXFG9 $39 Foreground Transmit Buffer 9

MSCAN_TXFG10 $3A Foreground Transmit Buffer 10

MSCAN_TXFG11 $3B Foreground Transmit Buffer 11

MSCAN_TXFG12 $3C Foreground Transmit Buffer 12

MSCAN_TXFG13 $3D Foreground Transmit Buffer 13

MSCAN_TXFG14 $3E Foreground Transmit Buffer 14

MSCAN_TXFG15 $3F Foreground Transmit Buffer 15

Reserved

Table 4-30 MSCAN Registers Address Map (Continued)

(MSCAN_BASE = $00 F800)