Datasheet

56F8036 Data Sheet, Rev. 6

Freescale Semiconductor 65

5.6.3 Interrupt Priority Register 2 (IPR2)

Figure 5-5 Interrupt Priority Register 2 (IPR2)

5.6.3.1 QSCI 0 Transmitter Empty Interrupt Priority Level (QSCI0_XMIT IPL)—

Bits 15–14

This field is used to set the interrupt priority level for the QSCI0 Transmitter Empty IRQ. This IRQ is

limited to priorities 0 through 2. It is disabled by default.

• 00 = IRQ disabled (default)

• 01 = IRQ is priority level 0

• 10 = IRQ is priority level 1

• 11 = IRQ is priority level 2

5.6.3.2 Reserved—Bits 13–10

This bit field is reserved. Each bit must be set to 0.

5.6.3.3 QSPI 0 Transmitter Empty Interrupt Priority Level (QSPI0_XMIT IPL)—

Bits 9–8

This field is used to set the interrupt priority level for the QSPI0 Transmitter Empty IRQ. This IRQ is

limited to priorities 0 through 2. It is disabled by default.

• 00 = IRQ disabled (default)

• 01 = IRQ is priority level 0

• 10 = IRQ is priority level 1

• 11 = IRQ is priority level 2

5.6.3.4 QSPI 0 Receiver Full Interrupt Priority Level (QSPI0_RCV IPL)—Bits 7–6

This field is used to set the interrupt priority level for the QSPI0 Receiver Full IRQ. This IRQ is limited

to priorities 0 through 2. It is disabled by default.

• 00 = IRQ disabled (default)

• 01 = IRQ is priority level 0

• 10 = IRQ is priority level 1

• 11 = IRQ is priority level 2

Base + $2

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Read

QSCI0_XMIT

IPL

0 0 0 0

QSPI0_XMIT

IPL

QSPI0_RCV

IPL

GPIOA IPL GPIOB IPL GPIOC IPL

Write

RESET

0000000000000000