Datasheet

Introduction
56F8036 Data Sheet, Rev. 6
Freescale Semiconductor 79
5.7.3 ITCN After Reset
After reset, all of the ITCN registers are in their default states. This means all interrupts are disabled,
except the core IRQs with fixed priorities:
• Illegal Instruction
• SW Interrupt 3
• HW Stack Overflow
• Misaligned Long Word Access
• SW Interrupt 2
• SW Interrupt 1
• SW Interrupt 0
• SW Interrupt LP
These interrupts are enabled at their fixed priority levels.
Part 6 System Integration Module (SIM)
6.1 Introduction
The SIM module is a system catchall for the glue logic that ties together the system-on-chip. It controls
distribution of resets and clocks and provides a number of control features. The System Integration
Module’s functions are discussed in more detail in the following sections.
6.2 Features
The SIM has the following features:
• Chip reset sequencing
• Core and peripheral clock control and distribution
• Stop/Wait mode control
• System status control
• Registers containing the JTAG ID of the chip
• Controls for programmable peripheral and GPIO connections
• Peripheral clocks for TMR and PWM with a high-speed (3X) option
• Power-saving clock gating for peripherals
• Three power modes (Run, Wait, Stop) to control power utilization
— Stop mode shuts down the 56800E core, system clock, and peripheral clock
— Wait mode shuts down the 56800E core and unnecessary system clock operation
— Run mode supports full device operation
• Controls the enable/disable functions of the 56800E core WAIT and STOP instructions with write protection
capability
• Controls the enable/disable functions of Large Regulator Standby mode with write protection capability