Datasheet

56F8037/56F8027 Data Sheet, Rev. 8

Freescale Semiconductor 109

6.3.12.6 Quad Timer B, Channel 3 Clock Stop Disable (TB3_SD)—Bit 7

• 0 = The clock is disabled during Stop mode

• 1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE1

6.3.12.7 Quad Timer B, Channel 2 Clock Stop Disable (TB2_SD)—Bit 6

• 0 = The clock is disabled during Stop mode

• 1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE1

6.3.12.8 Quad Timer B, Channel 1 Clock Stop Disable (TB1_SD)—Bit 5

• 0 = The clock is disabled during Stop mode

• 1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE1

6.3.12.9 Quad Timer B, Channel 0 Clock Stop Disable (TB0_SD)—Bit 4

• 0 = The clock is disabled during Stop mode

• 1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE1

6.3.12.10 Quad Timer A, Channel 3 Clock Stop Disable (TA3_SD)—Bit 3

• 0 = The clock is disabled during Stop mode

• 1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE1

6.3.12.11 Quad Timer A, Channel 2 Clock Stop Disable (TA2_SD)—Bit 2

• 0 = The clock is disabled during Stop mode

• 1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE1

6.3.12.12 Quad Timer A, Channel 1 Clock Stop Disable (TA1_SD)—Bit 1

• 0 = The clock is disabled during Stop mode

• 1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE1

6.3.12.13 Quad Timer A, Channel 0 Clock Stop Disable (TA0_SD)—Bit 0

• 0 = The clock is disabled during Stop mode

• 1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE1

6.3.13 I/O Short Address Location Register High (SIM_IOSAHI)

In I/O short address mode, the instruction specifies only 6 LSBs of the effective address; the upper 18 bits

are “hard coded” to a specific area of memory. This scheme allows efficient access to a 64-location area

in peripheral space with single word instruction. Short address location registers specify the upper 18 bits