Datasheet

56F8037/56F8027 Data Sheet, Rev. 8
56 Freescale Semiconductor
Table 4-11 Analog-to-Digital Converter Registers Address Map
(ADC_BASE = $00 F080)
Register Acronym Address Offset Register Description
ADC_CTRL1 $0 Control Register 1
ADC_CTRL2 $1 Control Register 2
ADC_ZXCTRL $2 Zero Crossing Control Register
ADC_CLIST 1 $3 Channel List Register 1
ADC_CLIST 2 $4 Channel List Register 2
ADC_CLIST 3 $5 Channel List Register 3
ADC_CLIST 4 $6 Channel List Register 4
ADC_SDIS $7 Sample Disable Register
ADC_STAT $8 Status Register
ADC_RDY $9 Conversion Ready Register
ADC_LIMSTAT $A Limit Status Register
ADC_ZXSTAT $B Zero Crossing Status Register
ADC_RSLT0 $C Result Register 0
ADC_RSLT1 $D Result Register 1
ADC_RSLT2 $E Result Register 2
ADC_RSLT3 $F Result Register 3
ADC_RSLT4 $10 Result Register 4
ADC_RSLT5 $11 Result Register 5
ADC_RSLT6 $12 Result Register 6
ADC_RSLT7 $13 Result Register 7
ADC_RSLT8 $14 Result Register 8
ADC_RSLT9 $15 Result Register 9
ADC_RSLT10 $16 Result Register 10
ADC_RSLT11 $17 Result Register 11
ADC_RSLT12 $18 Result Register 12
ADC_RSLT13 $19 Result Register 13
ADC_RSLT14 $1A Result Register 14
ADC_RSLT15 $1B Result Register 15
ADC_LOLIM0 $1C Low Limit Register 0
ADC_LOLIM1 $1D Low Limit Register 1
ADC_LOLIM2 $1E Low Limit Register 2
ADC_LOLIM3 $1F Low Limit Register 3
ADC_LOLIM4 $20 Low Limit Register 4
ADC_LOLIM5 $21 Low Limit Register 5
ADC_LOLIM6 $22 Low Limit Register 6
ADC_LOLIM7 $23 Low Limit Register 7