Datasheet

Peripheral Memory-Mapped Registers

56F8037/56F8027 Data Sheet, Rev. 8

Freescale Semiconductor 61

GPIOA_IPEND $7 Interrupt Pending Register

GPIOA_IEDGE $8 Interrupt Edge-Sensitive Register

GPIOA_PPOUTM $9 Push-Pull Output Mode Control Register

GPIOA_RDATA $A Raw Data Input Register

GPIOA_DRIVE $B Output Drive Strength Control Register

Table 4-19 GPIOB Registers Address Map

(GPIOB_BASE = $00 F160)

GPIOB_PUPEN $0 Pull-up Enable Register

GPIOB_DATA $1 Data Register

GPIOB_DDIR $2 Data Direction Register

GPIOB_PEREN $3 Peripheral Enable Register

GPIOB_IASSRT $4 Interrupt Assert Register

GPIOB_IEN $5 Interrupt Enable Register

GPIOB_IPOL $6 Interrupt Polarity Register

GPIOB_IPEND $7 Interrupt Pending Register

GPIOB_IEDGE $8 Interrupt Edge-Sensitive Register

GPIOB_PPOUTM $9 Push-Pull Output Mode Control Register

GPIOB_RDATA $A Raw Data Input Register

GPIOB_DRIVE $B Output Drive Strength Control Register

Table 4-20 GPIOC Registers Address Map

(GPIOC_BASE = $00 F170)

GPIOC_PUPEN $0 Pull-up Enable Register

GPIOC_DATA $1 Data Register

GPIOC_DDIR $2 Data Direction Register

GPIOC_PEREN $3 Peripheral Enable Register

GPIOC_IASSRT $4 Interrupt Assert Register

GPIOC_IEN $5 Interrupt Enable Register

GPIOC_IPOL $6 Interrupt Polarity Register

GPIOC_IPEND $7 Interrupt Pending Register

GPIOC_IEDGE $8 Interrupt Edge-Sensitive Register

GPIOC_PPOUTM $9 Push-Pull Output Mode Control Register

GPIOC_RDATA $A Raw Data Input Register

GPIOC_DRIVE $B Output Drive Strength Control Register

Table 4-18 GPIOA Registers Address Map (Continued)

(GPIOA_BASE = $00 F150)

Address Offset Register Description