Datasheet

MC56F825x/MC56F824x Product Brief, Rev. 2
Preliminary
Features
Freescale Semiconductor12
2.5.13 PLL
• Phase-locked loop (PLL) providing a high-speed clock to the core and peripherals
—2 system clock provided to quad timers and SCIs
— Loss of lock interrupt
— Loss of reference clock interrupt
2.5.14 Clock source
• Clock sources
— On-chip relaxation oscillator with two user-selectable frequencies: 400 kHz for low speed
mode, 8 MHz for normal operation
— External clock: crystal oscillator, ceramic resonator, and external clock source
2.5.15 CRC
• Cyclic redundancy check (CRC) generator
— Hardware CRC generator circuit using 16-bit shift register
— CRC16-CCITT compliance with 16 + 12 + 5 + 1 polynomial
— Error detection for all single, double, odd, and most multi-bit errors
— Programmable initial seed value
— High-speed hardware CRC calculation
— Optional feature to transpose input data and CRC result via transpose register—required on
applications where bytes are in LSB (least significant bit) format
2.5.16 GPIO
• Up to 54 general-purpose I/O (GPIO) pins
— 5 V tolerant I/O
— Individual control for each pin to be in peripheral or GPIO mode
— Individual input/output direction control for each pin in GPIO mode
— Individual control for each output pin to be in push-pull mode or open-drain mode
— Hysteresis and configurable pullup device on all input pins
— Ability to generate interrupt with programmable rising or falling edge and software interrupt
— Configurable drive strength: 4 mA / 8 mA sink/source current
2.5.17 JTAG/EOnCE
• JTAG/EOnCE debug programming interface for real-time debugging
— IEEE 1149.1 Joint Test Action Group (JTAG) interface
— EOnCE interface for real-time debugging