56F8345/56F8145 Data Sheet Preliminary Technical Data 56F8300 16-bit Digital Signal Controllers MC56F8345 Rev. 17 01/2007 freescale.
Document Revision History Version History Description of Change Rev 1.0 Pre-Release version, Alpha customers only Rev 2.0 Initial Public Release Rev 3.0 Corrected typo in Table 10-4, Flash Endurance is 10,000 cycles. Addressed additional grammar issues. Rev 4.0 Added “Typical Min” values to Table 10-16. Edited grammar, spelling, consistency of language throughout family.
Document Revision History (Continued) Version History Description of Change Rev 15.0 Updated JTAG ID in Section 6.5.4. Added information/corrected state during reset in Table 2-2. Clarified external reference crystal frequency for PLL in Table 10-14 by increasing maximum value to 8.4MHz. Rev 16.0 Replaced “Tri-stated” with an explanation in State During Reset column in Table 2-2. Rev.
56F8345 Technical Data, Rev.
6F8345/56F8145 General Description Note: Features in italics are NOT available in the 56F8145 device.
Table of Contents Part 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1 1.2 1.3 1.4 1.5 1.6 56F8345/56F8145 Features . . . . . . . . . . . .7 Device Description. . . . . . . . . . . . . . . . . . . .9 Award-Winning Development Environment11 Architecture Block Diagram . . . . . . . . . . . .12 Product Documentation . . . . . . . . . . . . . . .16 Data Sheet Conventions . . . . . . . . . . . . . .16 Part 2 Signal/Connection Descriptions . . . . 17 2.1 2.2 Introduction . . . . . . . . . . .
56F8345/56F8145 Features Part 1 Overview 1.1 56F8345/56F8145 Features 1.1.1 • • • • • • • • • • • • • • 1.1.
1.1.3 Memory Note: Features in italics are NOT available in the 56F8145 device. • • • Harvard architecture permits as many as three simultaneous accesses to program and data memory Flash security protection feature On-chip memory, including a low-cost, high-volume Flash solution — 128KB of Program Flash — 4KB of Program RAM — 8KB of Data Flash — 8KB of Data RAM — 8KB of Boot Flash • 1.1.
Device Description • • • • • • • 1.1.
program the main Program and Data Flash memory areas. Both Program and Data Flash memories can be independently bulk erased or erased in pages. Program Flash page erase size is 1KB. Boot and Data Flash page erase size is 512 bytes. The Boot Flash memory can also be either bulk or page erased. A key application-specific feature of the 56F8345 is the inclusion of two Pulse Width Modulator (PWM) modules.
Award-Winning Development Environment synchronous pulse width control (0% to 100% modulation) is supported. The device is capable of controlling most motor types: ACIM (AC Induction Motors); both BDC and BLDC (Brush and Brushless DC motors); SRM and VRM (Switched and Variable Reluctance Motors); and stepper motors. The PWM incorporates fault protection and cycle-by-cycle current limiting with sufficient output drive capability to directly drive standard optoisolators.
1.4 Architecture Block Diagram Note: Features in italics are NOT available in the 56F8145 device and are shaded in the following figures. The 56F8345/56F8145 architecture is shown in Figure 1-1 and Figure 1-2. Figure 1-1 illustrates how the 56800E system buses communicate with internal memories and the IPBus Bridge. Table 1-2 lists the internal buses in the 56800E architecture and provides a brief description of their function.
Architecture Block Diagram 5 JTAG / EOnCE Boot Flash pdb_m[15:0] pab[20:0] Program Flash cdbw[31:0] Program RAM 56800E EMI* CHIP TAP Controller 11 4 6 TAP Linking Module xab1[23:0] xab2[23:0] Address Data Control Data RAM Data Flash External JTAG Port cdbr_m[31:0] xdb2_m[15:0 IPBus Bridge Flash Memory Module NOT available on the 56F8145 device.
To/From IPBus Bridge Interrupt Controller CLKGEN (OSC / PLL) Low-Voltage Interrupt Timer A POR & LVI 4 System POR Quadrature Decoder 0 4 RESET SIM Timer D COP Reset Timer B 4 COP 2 FlexCAN Quadrature Decoder 1 SPI1 13 PWMA SYNC Output GPIOA 13 PWMB GPIOB SYNC Output GPIOC ch3i ch2i 2 Timer C GPIOD ch3o ch2o GPIOE GPIOF 4 2 SPI0 8 ADCA SCI0 TEMP_SENSE 2 8 ADCB SCI1 IPBus NOT available on the 56F8145 device.
Architecture Block Diagram Table 1-2 Bus Signal Names Name Function Program Memory Interface pdb_m[15:0] Program data bus for instruction word fetches or read operations. cdbw[15:0] Primary core data bus used for program memory writes. (Only these 16 bits of the cdbw[31:0] bus are used for writes to program memory.) pab[20:0] Program memory address bus. Data is returned on pdb_m bus. Primary Data Memory Interface Bus cdbr_m[31:0] Primary core data bus for memory reads. Addressed via xab1 bus.
1.5 Product Documentation The documents listed in Table 1-3 are required for a complete description and proper design with the 56F8345 and 56F8145 devices. Documentation is available from local Freescale distributors, Freescale Semiconductor sales offices, Freescale Literature Distribution Centers, or online at http://www.freescale.com.
Introduction Part 2 Signal/Connection Descriptions 2.1 Introduction The input and output signals of the 56F8345 and 56F8145 are organized into functional groups, as detailed in Table 2-1 and as illustrated in Figure 2-1. In Table 2-2, each table row describes the signal or signals present on a pin.
Power VDD_IO Power VDDA_ADC Power VDDA_OSC_PLL Ground VSS Ground VSSA_ADC OCR_DIS Other Supply Ports VCAP1 - VCAP4 VPP1 & VPP2 CLKMODE PLL and Clock EXTAL XTAL CLKO 7 1 1 1 1 5 1 1 1 56F8345 1 1 1 4 2 1 1 1 1 1 1 1 1 1 1 *External A8 - A13 (GPIOA0 - 5) Address Bus or GPIO GPIOB0-4 (A16 - 20) *External D7 - D10 (GPIOF0 - 3) 6 5 6 3 4 Data Bus 6 4 3 4 *External Bus Control GPIOD0 - 5 (CS2 - 7) 8 6 5 8 1 TXD0 (GPIOE0) SCI0 or GPIOE RXD0 (GPIOE1) SCI1 or GPIO TXD1 (
Introduction Power VDD_IO Power VDDA_ADC Power VDDA_OSC_PLL Ground VSS Ground VSSA_ADC OCR_DIS Other Supply Ports VCAP1 - VCAP4 VPP1 & VPP2 CLKMODE PLL and Clock EXTAL XTAL CLKO 7 1 1 1 1 5 1 1 1 4 2 1 56F8145 1 1 1 1 1 1 1 1 1 1 1 1 *External A8 - A13 (GPIOA0 - 5) Address Bus or GPIO GPIOB0-4 (A16 - 20) *External D7 - D10 (GPIOF0 - 3) Data Bus Bus Control GPIOD0 - 5 (CS2 - 7) 5 3 6 4 3 8 6 5 8 TXD0 (GPIOE0) SCI0 or GPIOE RXD0 (GPIOE1) SCI1 or GPIO TXD1 (GPIOD6) RX
2.2 Signal Pins After reset, each pin is configured for its primary function (listed first). Any alternate functionality must be programmed. EMI is not functional in this package; since only part of the address/data bus is bonded out, use as GPIO pins. Note: Signals in italics are NOT available in the 56F8145 device. If the “State During Reset” lists more than one state for a pin, the first state is the actual reset state.
Signal Pins Table 2-2 Signal and Package Information for the 128-Pin LQFP Signal Name Pin No. Type VSSA_ADC 95 Supply OCR_DIS 71 Input State During Reset Signal Description ADC Analog Ground — This pin supplies an analog ground to the ADC modules. Input On-Chip Regulator Disable — Tie this pin to VSS to enable the on-chip regulator Tie this pin to VDD to disable the on-chip regulator This pin is intended to be a static DC signal from power-up to shut down.
Table 2-2 Signal and Package Information for the 128-Pin LQFP Signal Name Pin No. Type CLKO 6 Output State During Reset In reset, output is disabled Signal Description Clock Output — This pin outputs a buffered clock signal. Using the SIM CLKO Select Register (SIM_CLKOSR), this pin can be programmed as any of the following: disabled, CLK_MSTR (system clock), IPBus clock, oscillator output, prescaler clock and postscaler clock. Other signals are also available for test purposes. See Part 6.5.
Signal Pins Table 2-2 Signal and Package Information for the 128-Pin LQFP Signal Name Pin No. Type State During Reset GPIOB4 31 Schmitt Input/ Output Input, pull-up enabled Signal Description Port B GPIO — This GPIO pin can be individually programmed as an input or output pin. (A20) Output Address Bus — A20 specifies one of the address lines for external program or data memory accesses.
Table 2-2 Signal and Package Information for the 128-Pin LQFP Signal Name Pin No. Type GPIOD0 42 Input/ Output State During Reset Input, pull-up enabled Output (CS2) GPIOD1 (CS3) 43 GPIOD2 (CS4) 44 GPIOD3 (CS5) 45 GPIOD4 (CS6) 46 GPIOD5 (CS7) 47 TXD0 7 Signal Description Port D GPIO — These six GPIO pins can be individually programmed as input or output pins.
Signal Pins Table 2-2 Signal and Package Information for the 128-Pin LQFP Signal Name Pin No. Type RXD1 41 Input (GPIOD7) Input/ Output State During Reset Input, pull-up enabled Signal Description Receive Data — SCI1 receive data input Port D GPIO — This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is SCI input. To deactivate the internal pull-up resistor, clear bit 7 in the GPIOD_PUR register.
Table 2-2 Signal and Package Information for the 128-Pin LQFP Signal Name Pin No. Type TRST 114 Schmitt Input State During Reset Input, pulled high internally Signal Description Test Reset — As an input, a low signal on this pin provides a reset signal to the JTAG TAP controller. To ensure complete hardware reset, TRST should be asserted whenever RESET is asserted.
Signal Pins Table 2-2 Signal and Package Information for the 128-Pin LQFP Signal Name Pin No. Type INDEX0 1 Schmitt Input State During Reset Input, pull-up enabled Signal Description Index — Quadrature Decoder 0, INDEX input (TA2) Schmitt Input/ Output TA2 — Timer A, Channel 2 (GPIOC6) Schmitt Input/ Output Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is INDEX0.
Table 2-2 Signal and Package Information for the 128-Pin LQFP Signal Name Pin No. Type MOSI0 126 Input/ Output (GPIOE5) State During Reset In reset, output is disabled, pull-up is enabled Input/ Output Signal Description SPI 0 Master Out/Slave In — This serial data pin is an output from a master device and an input to a slave device. The master device places data on the MOSI line a half-cycle before the clock edge the slave device uses to latch the data.
Signal Pins Table 2-2 Signal and Package Information for the 128-Pin LQFP Signal Name Pin No. Type PHASEA1 9 Schmitt Input State During Reset Input, pull-up enabled Signal Description Phase A1 — Quadrature Decoder 1, PHASEA input for decoder 1. (TB0) Schmitt Input/ Output TB0 — Timer B, Channel 0 (SCLK1) Schmitt Input/ Output SPI 1 Serial Clock — In the master mode, this pin serves as an output, clocking slaved listeners. In slave mode, this pin serves as the data clock input.
Table 2-2 Signal and Package Information for the 128-Pin LQFP Signal Name Pin No. Type INDEX1 11 Schmitt Input State During Reset Input, pull-up enabled Signal Description Index1 — Quadrature Decoder 1, INDEX input (TB2) Schmitt Input/ Output TB2 — Timer B, Channel 2 (MISO1) Schmitt Input/ Output SPI 1 Master In/Slave Out — This serial data pin is an input to a master device and output from a slave device.
Signal Pins Table 2-2 Signal and Package Information for the 128-Pin LQFP Signal Name Pin No. Type HOME1 12 Schmitt Input State During Reset Input, pull-up enabled Signal Description Home — Quadrature Decoder 1, HOME input (TB3) Schmitt Input/ Output TB3 — Timer B, Channel 3 (SS1) Schmitt Input SPI 1 Slave Select — In the master mode, this pin is used to arbitrate multiple masters. In slave mode, this pin is used to select the slave.
Table 2-2 Signal and Package Information for the 128-Pin LQFP Signal Name Pin No. Type FAULTA0 67 Schmitt Input FAULTA1 68 FAULTA2 69 FAULTA3 70 State During Reset Input, pull-up enabled Signal Description FAULTA0 - 2 — These three fault input pins are used for disabling selected PWMA outputs in cases where fault conditions originate off-chip. To deactivate the internal pull-up resistor, set the PWMA0 bit in the SIM_PUDR register. See Part 6.5.6 for details.
Signal Pins Table 2-2 Signal and Package Information for the 128-Pin LQFP State During Reset Signal Name Pin No. Type ANA4 84 Input Analog Input ANA4 - 7 — Analog inputs to ADC A, channel 1 ANA5 85 ANA6 86 ANA7 87 VREFH 93 Input Analog Input VREFH — Analog Reference Voltage High. VREFH must be less than or equal to VDDA_ADC.
Table 2-2 Signal and Package Information for the 128-Pin LQFP Signal Name Pin No. Type State During Reset CAN_TX 120 Open Drain Output Open Drain Output Signal Description FlexCAN Transmit Data — CAN output with internal pull-up enable at reset.* * Note: If a pin is configured as open drain output mode, internal pull-up will automatically be disabled when it outputs low.
Signal Pins Table 2-2 Signal and Package Information for the 128-Pin LQFP Signal Name Pin No. Type RESET 78 Schmitt Input State During Reset Input, pull-up enabled Signal Description Reset — This input is a direct hardware reset on the processor. When RESET is asserted low, the device is initialized and placed in the reset state. A Schmitt trigger input is used for noise immunity.
Part 3 On-Chip Clock Synthesis (OCCS) 3.1 Introduction Refer to the OCCS chapter of the 56F8300 Peripheral User Manual for a full description of the OCCS. The material contained here identifies the specific features of the OCCS design. Figure 3-1 shows the specific OCCS block diagram to reference in the OCCS chapter of the 56F8300 Peripheral User Manual.
External Clock Operation The crystal and associated components should be mounted as near as possible to the EXTAL and XTAL pins to minimize output distortion and start-up stabilization time.
Resonator Frequency = 4 - 8MHz (optimized for 8MHz) 3 Terminal 2 Terminal EXTAL XTAL Rz CL1 EXTAL XTAL Rz Sample External Ceramic Resonator Parameters: Rz = 750 KΩ CLKMODE = 0 CL2 C1 C2 Figure 3-3 Connecting a Ceramic Resonator Note: The OCCS_COHL bit must be set to 0 when a ceramic resonator is used. The reset condition on the OCCS_COHL bit is 0. Please see the COHL bit in the Oscillator Control (OSCTL) register, discussed in the 56F8300 Peripheral User’s Manual. 3.2.
Program Map RAM and Flash memories are used in both spaces. This section provides memory maps for: • • Program Address Space, including the Interrupt Vector Table Data Address Space, including the EOnCE Memory and Peripheral Memory Maps On-chip memory sizes for each device are summarized in Table 4-1. Flash memories’ restrictions are identified in the “Use Restrictions” column of Table 4-1. Note: Data Flash and Program RAM are NOT available on the 56F8145 device.
Table 4-2 OMR MB/MA Value at Reset1 (Continued) OMR MB = Flash Secured State2,3 OMR MA = EXTBOOT Pin 1 1 Chip Operating Mode Mode 1 – External Boot; Flash Memory is not secured; EMI configuration is determined by the state of the EMI_MODE pin 1. Information in shaded areas not applicable to 56F8345/56F8145. 2. This bit is only configured at reset. If the Flash secured state changes, this will not be reflected in MB until the next reset. 3. Changing MB in software will not affect Flash memory security.
Interrupt Vector Table Table 4-4 Program Memory Map at Reset Begin/End Address Mode 0 (MA = 0) Mode 11 (MA = 1) Internal Boot External Boot Internal Boot 16-Bit External Address Bus P:$1F FFFF P:$10 0000 External Program Memory5 EMI_MODE = 02, 3 16-Bit External Address Bus External Program Memory5 P:$0F FFFF P:$03 0000 P:$02 FFFF P:$02 F800 On-Chip Program RAM 4KB On-Chip Program RAM 4KB P:$02 F7FF P:$02 1000 EMI_MODE = 14 20-Bit External Address Bus External Program Memory5 External Program R
JMP instructions. All other entries must contain JSR instructions. Note: PWMA, FlexCAN, Quadrature Decoder 1, and Quad Timers B and D are NOT available on the 56F8145 device.
Interrupt Vector Table Table 4-5 Interrupt Vector Table Contents1 (Continued) Peripheral Vector Number Priority Level Vector Base Address + Interrupt Function FLEXCAN 29 0-2 P:$3A FLEXCAN Message Buffer Interrupt GPIOF 30 0-2 P:$3C GPIO F GPIOE 31 0-2 P:$3E GPIO E GPIOD 32 0-2 P:$40 GPIO D GPIOC 33 0-2 P:$42 GPIO C GPIOB 34 0-2 P:$44 GPIO B GPIOA 35 0-2 P:$46 GPIO A Reserved SPI1 38 0-2 P:$4C SPI 1 Receiver Full SPI1 39 0-2 P:$4E SPI 1 Transmitter Empty SPI
Table 4-5 Interrupt Vector Table Contents1 (Continued) Peripheral Vector Number Priority Level Vector Base Address + Interrupt Function TMRB 60 0-2 P:$78 Timer B, Channel 0 TMRB 61 0-2 P:$7A Timer B, Channel 1 TMRB 62 0-2 P:$7C Timer B, Channel 2 TMRB 63 0-2 P:$7E Timer B, Channel 3 TMRA 64 0-2 P:$80 Timer A, Channel 0 TMRA 65 0-2 P:$82 Timer A, Channel 1 TMRA 66 0-2 P:$84 Timer A,Channel 2 TMRA 67 0-2 P:$86 Timer A, Channel 3 SCI0 68 0-2 P:$88 SCI 0 Transmit
Data Map 4.4 Data Map Note: Data Flash is NOT available on the 56F8145 device.
Data Memory Program Memory BOOT_FLASH_START + $1FFF FM_BASE + $14 8KB Boot BOOT_FLASH_START = $02_0000 FM_BASE + $00 Reserved Banked Registers Unbanked Registers DATA_FLASH_START + $0FFF 8KB DATA_FLASH_START + $0000 Configure Field FM_PROG_MEM_TOP = $00_FFFF Block 0 Odd Block 0 Even Note: Data Flash is NOT available in the 56F8145 device. ...
Peripheral Memory Mapped Registers Table 4-8 EOnCE Memory Map (Continued) Address Register Acronym Register Name Reserved X:$FF FF90 OBMSK (32 bits) Breakpoint 1 Unit [0] Mask Register X:$FF FF91 — Breakpoint 1 Unit [0] Mask Register X:$FF FF92 OBAR2 (32 bits) Breakpoint 2 Unit [0] Address Register X:$FF FF93 — Breakpoint 2 Unit [0] Address Register X:$FF FF94 OBAR1 (24 bits) Breakpoint 1 Unit [0] Address Register X:$FF FF95 — Breakpoint 1 Unit [0] Address Register X:$FF FF96 OBCR (24
Table 4-9 Data Memory Peripheral Base Address Map Summary Peripheral Prefix Base Address Table Number External Memory Interface EMI X:$00 F020 4-10 Timer A TMRA X:$00 F040 4-11 Timer B TMRB X:$00 F080 4-12 Timer C TMRC X:$00 F0C0 4-13 Timer D TMRD X:$00 F100 4-14 PWM A PWMA X:$00 F140 4-15 PWM B PWMB X:$00 F160 4-16 Quadrature Decoder 0 DEC0 X:$00 F180 4-17 Quadrature Decoder 1 DEC1 X:$00 F190 4-18 ITCN ITCN X:$00 F1A0 4-19 ADC A ADCA X:$00 F200 4-20 ADC B AD
Peripheral Memory Mapped Registers Table 4-10 External Memory Integration Registers Address Map (EMI_BASE = $00 F020) Address Offset Register Description Reset Values CSBAR 0 $0 Chip Select Base Address Register 0 0 x 0004 = 64K since EXTBOOT = EMI_MODE =0 CSBAR 1 $1 Chip Select Base Address Register 1 0 x 0004 = 64K since EMI_MODE = 0 CSBAR 2 $2 Chip Select Base Address Register 2 CSBAR 3 $3 Chip Select Base Address Register 3 CSBAR 4 $4 Chip Select Base Address Register 4 CSBAR 5 $5
Table 4-11 Quad Timer A Registers Address Map (Continued) (TMRA_BASE = $00 F040) Register Acronym Address Offset Register Description TMRA0_CMP2 $1 Compare Register 2 TMRA0_CAP $2 Capture Register TMRA0_LOAD $3 Load Register TMRA0_HOLD $4 Hold Register TMRA0_CNTR $5 Counter Register TMRA0_CTRL $6 Control Register TMRA0_SCR $7 Status and Control Register TMRA0_CMPLD1 $8 Comparator Load Register 1 TMRA0_CMPLD2 $9 Comparator Load Register 2 TMRA0_COMSCR $A Comparator Status and
Peripheral Memory Mapped Registers Table 4-11 Quad Timer A Registers Address Map (Continued) (TMRA_BASE = $00 F040) Register Acronym Address Offset Register Description TMRA2_CMPLD2 $29 Comparator Load Register 2 TMRA2_COMSCR $2A Comparator Status and Control Register Reserved TMRA3_CMP1 $30 Compare Register 1 TMRA3_CMP2 $31 Compare Register 2 TMRA3_CAP $32 Capture Register TMRA3_LOAD $33 Load Register TMRA3_HOLD $34 Hold Register TMRA3_CNTR $35 Counter Register TMRA3_CTRL $36
Table 4-12 Quad Timer B Registers Address Map (Continued) (TMRB_BASE = $00 F080) Quad Timer B is NOT available in the 56F8145 device Register Acronym Address Offset Register Description TMRB1_CMP2 $11 Compare Register 2 TMRB1_CAP $12 Capture Register TMRB1_LOAD $13 Load Register TMRB1_HOLD $14 Hold Register TMRB1_CNTR $15 Counter Register TMRB1_CTRL $16 Control Register TMRB1_SCR $17 Status and Control Register TMRB1_CMPLD1 $18 Comparator Load Register 1 TMRB1_CMPLD2 $19 Compara
Peripheral Memory Mapped Registers Table 4-12 Quad Timer B Registers Address Map (Continued) (TMRB_BASE = $00 F080) Quad Timer B is NOT available in the 56F8145 device Register Acronym Address Offset Register Description TMRB3_HOLD $34 Hold Register TMRB3_CNTR $35 Counter Register TMRB3_CTRL $36 Control Register TMRB3_SCR $37 Status and Control Register TMRB3_CMPLD1 $38 Comparator Load Register 1 TMRB3_CMPLD2 $39 Comparator Load Register 2 TMRB3_COMSCR $3A Comparator Status and Contr
Table 4-13 Quad Timer C Registers Address Map (Continued) (TMRC_BASE = $00 F0C0) Register Acronym Address Offset Register Description TMRC1_CMPLD2 $19 Comparator Load Register 2 TMRC1_COMSCR $1A Comparator Status and Control Register Reserved TMRC2_CMP1 $20 Compare Register 1 TMRC2_CMP2 $21 Compare Register 2 TMRC2_CAP $22 Capture Register TMRC2_LOAD $23 Load Register TMRC2_HOLD $24 Hold Register TMRC2_CNTR $25 Counter Register TMRC2_CTRL $26 Control Register TMRC2_SCR $27 St
Peripheral Memory Mapped Registers Table 4-14 Quad Timer D Registers Address Map (Continued) (TMRD_BASE = $00 F100) Quad Timer D is NOT available in the 56F8145 device Register Acronym Address Offset Register Description TMRD0_CAP $2 Capture Register TMRD0_LOAD $3 Load Register TMRD0_HOLD $4 Hold Register TMRD0_CNTR $5 Counter Register TMRD0_CTRL $6 Control Register TMRD0_SCR $7 Status and Control Register TMRD0_CMPLD1 $8 Comparator Load Register 1 TMRD0_CMPLD2 $9 Comparator Load
Table 4-14 Quad Timer D Registers Address Map (Continued) (TMRD_BASE = $00 F100) Quad Timer D is NOT available in the 56F8145 device Register Acronym TMRD2_COMSCR Address Offset $2A Register Description Comparator Status and Control Register Reserved TMRD3_CMP1 $30 Compare Register 1 TMRD3_CMP2 $31 Compare Register 2 TMRD3_CAP $32 Capture Register TMRD3_LOAD $33 Load Register TMRD3_HOLD $34 Hold Register TMRD3_CNTR $35 Counter Register TMRD3_CTRL $36 Control Register TMRD3_SCR $37
Peripheral Memory Mapped Registers Table 4-15 Pulse Width Modulator A Registers Address Map (Continued) (PWMA_BASE = $00 F140) PWMA is NOT available in the 56F8145 device Register Acronym Address Offset Register Description PWMA_PMDISMAP2 $E Disable Mapping Register 2 PWMA_PMCFG $F Configure Register PWMA_PMCCR $10 Channel Control Register PWMA_PMPORT $11 Port Register PWMA_PMICCR $12 PWM Internal Correction Control Register Table 4-16 Pulse Width Modulator B Registers Address Map (PWMB_B
Table 4-17 Quadrature Decoder 0 Registers Address Map (DEC0_BASE = $00 F180) Register Acronym Address Offset Register Description DEC0_DECCR $0 Decoder Control Register DEC0_FIR $1 Filter Interval Register DEC0_WTR $2 Watchdog Time-out Register DEC0_POSD $3 Position Difference Counter Register DEC0_POSDH $4 Position Difference Counter Hold Register DEC0_REV $5 Revolution Counter Register DEC0_REVH $6 Revolution Hold Register DEC0_UPOS $7 Upper Position Counter Register DEC0_LPOS
Peripheral Memory Mapped Registers Table 4-18 Quadrature Decoder 1 Registers Address Map (Continued) (DEC1_BASE = $00 F190) Quadrature Decoder 1 is NOT available in the 56F8145 device Register Acronym DEC1_IMR Address Offset $D Register Description Input Monitor Register Table 4-19 Interrupt Control Registers Address Map (ITCN_BASE = $00 F1A0) Register Acronym Address Offset Register Description IPR 0 $0 Interrupt Priority Register 0 IPR 1 $1 Interrupt Priority Register 1 IPR 2 $2 Interrupt P
Table 4-20 Analog-to-Digital Converter Registers Address Map (ADCA_BASE = $00 F200) Register Acronym Address Offset Register Description ADCA_CR1 $0 Control Register 1 ADCA_CR2 $1 Control Register 2 ADCA_ZCC $2 Zero Crossing Control Register ADCA_LST 1 $3 Channel List Register 1 ADCA_LST 2 $4 Channel List Register 2 ADCA_SDIS $5 Sample Disable Register ADCA_STAT $6 Status Register ADCA_LSTAT $7 Limit Status Register ADCA_ZCSTAT $8 Zero Crossing Status Register ADCA_RSLT 0 $9
Peripheral Memory Mapped Registers Table 4-20 Analog-to-Digital Converter Registers Address Map (Continued) (ADCA_BASE = $00 F200) Register Acronym Address Offset Register Description ADCA_HLMT 7 $20 High Limit Register 7 ADCA_OFS 0 $21 Offset Register 0 ADCA_OFS 1 $22 Offset Register 1 ADCA_OFS 2 $23 Offset Register 2 ADCA_OFS 3 $24 Offset Register 3 ADCA_OFS 4 $25 Offset Register 4 ADCA_OFS 5 $26 Offset Register 5 ADCA_OFS 6 $27 Offset Register 6 ADCA_OFS 7 $28 Offset Registe
Table 4-21 Analog-to-Digital Converter Registers Address Map (Continued) (ADCB_BASE = $00 F240) Register Acronym Address Offset Register Description ADCB_LLMT 1 $12 Low Limit Register 1 ADCB_LLMT 2 $13 Low Limit Register 2 ADCB_LLMT 3 $14 Low Limit Register 3 ADCB_LLMT 4 $15 Low Limit Register 4 ADCB_LLMT 5 $16 Low Limit Register 5 ADCB_LLMT 6 $17 Low Limit Register 6 ADCB_LLMT 7 $18 Low Limit Register 7 ADCB_HLMT 0 $19 High Limit Register 0 ADCB_HLMT 1 $1A High Limit Register 1
Peripheral Memory Mapped Registers Table 4-23 Serial Communication Interface 0 Registers Address Map (SCI0_BASE = $00 F280) Register Acronym Address Offset Register Description SCI0_SCIBR $0 Baud Rate Register SCI0_SCICR $1 Control Register Reserved SCI0_SCISR $3 Status Register SCI0_SCIDR $4 Data Register Table 4-24 Serial Communication Interface 1 Registers Address Map (SCI1_BASE = $00 F290) Register Acronym Address Offset Register Description SCI1_SCIBR $0 Baud Rate Register SCI1_SC
Table 4-26 Serial Peripheral Interface 1 Registers Address Map (Continued) (SPI1_BASE = $00 F2B0) Register Acronym SPI1_SPDTR Address Offset $3 Register Description Data Transmitter Register Table 4-27 Computer Operating Properly Registers Address Map (COP_BASE = $00 F2C0) Register Acronym Address Offset Register Description COPCTL $0 Control Register COPTO $1 Time-Out Register COPCTR $2 Counter Register Table 4-28 Clock Generation Module Registers Address Map (CLKGEN_BASE = $00 F2D0) Registe
Peripheral Memory Mapped Registers Table 4-29 GPIOA Registers Address Map (Continued) (GPIOA_BASE = $00 F2E0) Register Acronym Address Offset Register Description Reset Value GPIOA_PPMODE $9 Push-Pull Mode Register 0 x 3FFF GPIOA_RAWDATA $A Raw Data Input Register — Table 4-30 GPIOB Registers Address Map (GPIOB_BASE = $00 F300) Register Acronym Address Offset Register Description Reset Value GPIOB_PUR $0 Pull-up Enable Register 0 x 00FF GPIOB_DR $1 Data Register 0 x 0000 GPIOB_DDR
Table 4-31 GPIOC Registers Address Map (Continued) (GPIOC_BASE = $00 F310) Register Acronym Address Offset GPIOC_RAWDATA $A Register Description Raw Data Input Register Reset Value — Table 4-32 GPIOD Registers Address Map (GPIOD_BASE = $00 F320) Register Acronym Address Offset Register Description Reset Value GPIOD_PUR $0 Pull-up Enable Register 0 x 1FFF GPIOD_DR $1 Data Register 0 x 0000 GPIOD_DDR $2 Data Direction Register 0 x 0000 GPIOD_PER $3 Peripheral Enable Register 0 x 1FC0
Peripheral Memory Mapped Registers Table 4-34 GPIOF Registers Address Map (GPIOF_BASE = $00 F340) Register Acronym Address Offset Register Description Reset Value GPIOF_PUR $0 Pull-up Enable Register 0 x FFFF GPIOF_DR $1 Data Register 0 x 0000 GPIOF_DDR $2 Data Direction Register 0 x 0000 GPIOF_PER $3 Peripheral Enable Register 0 x FFFF GPIOF_IAR $4 Interrupt Assert Register 0 x 0000 GPIOF_IENR $5 Interrupt Enable Register 0 x 0000 GPIOF_IPOLR $6 Interrupt Polarity Register 0
Table 4-36 Power Supervisor Registers Address Map (LVI_BASE = $00 F360) Register Acronym Address Offset Register Description LVI_CONTROL $0 Control Register LVI_STATUS $1 Status Register Table 4-37 Flash Module Registers Address Map (FM_BASE = $00 F400) Register Acronym Address Offset Register Description FMCLKD $0 Clock Divider Register FMMCR $1 Module Control Register Reserved FMSECH $3 Security High Half Register FMSECL $4 Security Low Half Register Reserved Reserved FMPROT $10
Peripheral Memory Mapped Registers Table 4-38 FlexCAN Registers Address Map (FC_BASE = $00 F800) FlexCAN is NOT available in the 56F8145 device Register Acronym FCMCR Address Offset $0 Register Description Module Configuration Register Reserved FCCTL0 $3 Control Register 0 Register FCCTL1 $4 Control Register 1 Register FCTMR $5 Free-Running Timer Register FCMAXMB $6 Maximum Message Buffer Configuration Register Reserved FCRXGMASK_H $8 Receive Global Mask High Register FCRXGMASK_L $9 Rec
Table 4-38 FlexCAN Registers Address Map (Continued) (FC_BASE = $00 F800) FlexCAN is NOT available in the 56F8145 device Register Acronym Address Offset Register Description FCMSB1_ID_HIGH $49 Message Buffer 1 ID High Register FCMSB1_ID_LOW $4A Message Buffer 1 ID Low Register FCMB1_DATA $4B Message Buffer 1 Data Register FCMB1_DATA $4C Message Buffer 1 Data Register FCMB1_DATA $4D Message Buffer 1 Data Register FCMB1_DATA $4E Message Buffer 1 Data Register Reserved FCMB2_CONTROL $50
Peripheral Memory Mapped Registers Table 4-38 FlexCAN Registers Address Map (Continued) (FC_BASE = $00 F800) FlexCAN is NOT available in the 56F8145 device Register Acronym Address Offset Register Description FCMB5_CONTROL $68 Message Buffer 5 Control / Status Register FCMB5_ID_HIGH $69 Message Buffer 5 ID High Register FCMB5_ID_LOW $6A Message Buffer 5 ID Low Register FCMB5_DATA $6B Message Buffer 5 Data Register FCMB5_DATA $6C Message Buffer 5 Data Register FCMB5_DATA $6D Message Buff
Table 4-38 FlexCAN Registers Address Map (Continued) (FC_BASE = $00 F800) FlexCAN is NOT available in the 56F8145 device Register Acronym Address Offset Register Description FCMB8_DATA $84 Message Buffer 8 Data Register FCMB8_DATA $85 Message Buffer 8 Data Register FCMB8_DATA $86 Message Buffer 8 Data Register Reserved FCMB9_CONTROL $88 Message Buffer 9 Control / Status Register FCMB9_ID_HIGH $89 Message Buffer 9 ID High Register FCMB9_ID_LOW $8A Message Buffer 9 ID Low Register FCMB9_D
Factory Programmed Memory Table 4-38 FlexCAN Registers Address Map (Continued) (FC_BASE = $00 F800) FlexCAN is NOT available in the 56F8145 device Register Acronym Address Offset Register Description FCMB12_DATA $A4 Message Buffer 12 Data Register FCMB12_DATA $A5 Message Buffer 12 Data Register FCMB12_DATA $A6 Message Buffer 12 Data Register Reserved FCMB13_CONTROL $A8 Message Buffer 13 Control / Status Register FCMB13_ID_HIGH $A9 Message Buffer 13 ID High Register FCMB13_ID_LOW $AA Mes
Data Flash (NOT available in the 56F8145) memories of the device. The 56F83xx SCI/CAN Bootloader User Manual (MC56F83xxBLUM) provides detailed information on this firmware. An application note, Production Flash Programming (AN1973), details how the Serial Bootloader program can be used to perform production Flash programming of the on-board Flash memories as well as other potential methods. Like all the Flash memory blocks, the Boot Flash can be erased and programmed by the user.
Functional Description 5.3.2 Interrupt Nesting Interrupt exceptions may be nested to allow an IRQ of higher priority than the current exception to be serviced. The following tables define the nesting requirements for each priority level. Table 5-1 Interrupt Mask Bit Definition SR[9]1 SR[8]1 0 0 Priorities 0, 1, 2, 3 None 0 1 Priorities 1, 2, 3 Priority 0 1 0 Priorities 2, 3 Priorities 0, 1 1 1 Priority 3 Priorities 0, 1, 2 Permitted Exceptions Masked Exceptions 1.
5.4 Block Diagram any0 Priority Level INT1 2 -> 4 Decode Level 0 82 -> 7 Priority Encoder 7 INT VAB CONTROL any3 Level 3 Priority Level INT82 IPIC IACK SR[9:8] 82 -> 7 Priority Encoder 7 PIC_EN 2 -> 4 Decode Figure 5-1 Interrupt Controller Block Diagram 5.5 Operating Modes The ITCN module design contains two major modes of operation: • • Functional Mode The ITCN is in this mode by default. Wait and Stop Modes During Wait and Stop modes, the system clocks and the 56800E core are turned off.
Register Descriptions 5.6 Register Descriptions A register address is the sum of a base address and an address offset. The base address is defined at the system level and the address offset is defined at the module level. The ITCN peripheral has 24 registers. Table 5-3 ITCN Register Summary (ITCN_BASE = $00F1A0) Register Acronym Base Address + Register Name Section Location IPR0 $0 Interrupt Priority Register 0 5.6.1 IPR1 $1 Interrupt Priority Register 1 5.6.
Add.
Register Descriptions Figure 5-2 ITCN Register Map Summary 5.6.1 Interrupt Priority Register 0 (IPR0) Base + $0 15 14 Read 0 0 13 12 BKPT_U0IPL 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STPCNT IPL Write RESET 0 0 0 0 0 0 Figure 5-3 Interrupt Priority Register 0 (IPR0) 5.6.1.1 Reserved—Bits 15–14 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 5.6.1.
5.6.2 Interrupt Priority Register 1 (IPR1) Base + $1 15 14 13 12 11 10 9 8 7 6 Read 0 0 0 0 0 0 0 0 0 0 5 4 RX_REG IPL 3 2 TX_REG IPL 1 0 TRBUF IPL Write RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 5-4 Interrupt Priority Register 1 (IPR1) 5.6.2.1 Reserved—Bits 15–6 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 5.6.2.
Register Descriptions • • 10 = IRQ is priority level 2 11 = IRQ is priority level 3 5.6.3 Interrupt Priority Register 2 (IPR2) Base + $2 15 14 13 12 11 10 9 8 7 6 Read FMCBE IPL FMCC IPL FMERR IPL LOCK IPL 5 4 0 0 LVI IPL 3 2 1 0 IRQB IPL IRQA IPL 0 0 Write RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 5-5 Interrupt Priority Register 2 (IPR2) 5.6.3.
• • 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.3.4 PLL Loss of Lock Interrupt Priority Level (LOCK IPL)—Bits 9–8 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.3.
Register Descriptions • • 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.4 Interrupt Priority Register 3 (IPR3) Base + $3 Read Write RESET 15 14 13 12 11 10 GPIOD IPL GPIOE IPL GPIOF IPL 0 0 0 0 0 0 9 8 FCMSGBUF IPL 0 0 7 6 FCWKUP IPL 0 0 5 4 FCERR IPL 0 0 3 2 1 0 0 0 0 0 FCBOFF IPL 0 0 Figure 5-6 Interrupt Priority Register 3 (IPR3) 5.6.4.
• • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.4.5 FlexCAN Wake Up Interrupt Priority Level (FCWKUP IPL)—Bits 7–6 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.4.
Register Descriptions 5.6.5 Interrupt Priority Register 4 (IPR4) Base + $4 Read 15 14 SPI0_RCV IPL Write RESET 0 0 13 12 SPI1_XMIT IPL 0 0 11 10 9 8 7 6 SPI1_RCV IPL 0 0 0 0 0 0 0 0 0 0 5 4 GPIOA IPL 0 0 3 2 GPIOB IPL 0 0 1 0 GPIOC IPL 0 0 Figure 5-7 Interrupt Priority Register 4 (IPR4) 5.6.5.1 SPI 0 Receiver Full Interrupt Priority Level (SPI0_RCV IPL)— Bits 15–14 This field is used to set the interrupt priority level for IRQs.
5.6.5.5 GPIOA Interrupt Priority Level (GPIOA IPL)—Bits 5–4 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.5.6 GPIOB Interrupt Priority Level (GPIOB IPL)—Bits 3–2 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
Register Descriptions • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.6.2 Quadrature Decoder 1 HOME Signal Transition or Watchdog Timer Interrupt Priority Level (DEC1_HIRQ IPL)—Bits 13–12 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default.
5.6.6.6 SCI 1 Transmitter Idle Interrupt Priority Level (SCI1_TIDL IPL)— Bits 5–4 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.6.7 SCI 1 Transmitter Empty Interrupt Priority Level (SCI1_XMIT IPL)— Bits 3–2 This field is used to set the interrupt priority level for IRQs.
Register Descriptions 5.6.7.1 Timer C, Channel 0 Interrupt Priority Level (TMRC0 IPL)— Bits 15–14 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.7.2 Timer D, Channel 3 Interrupt Priority Level (TMRD3 IPL)— Bits 13–12 This field is used to set the interrupt priority level for IRQs.
• • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.7.6 Reserved—Bits 5–4 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 5.6.7.7 Quadrature Decoder 0, INDEX Pulse Interrupt Priority Level (DEC0_XIRQ IPL)—Bits 3–2 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default.
Register Descriptions 5.6.8.2 Timer B, Channel 3 Interrupt Priority Level (TMRB3 IPL)—Bits 13–12 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.8.3 Timer B, Channel 2 Interrupt Priority Level (TMRB2 IPL)—Bits 11–10 This field is used to set the interrupt priority level for IRQs.
• • 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.8.7 Timer C, Channel 2 Interrupt Priority Level (TMRC2 IPL)—Bits 3–2 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.8.
Register Descriptions • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.9.3 Reserved—Bits 11–10 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 5.6.9.4 SCI0 Transmitter Idle Interrupt Priority Level (SCI0_TIDL IPL)— Bits 9–8 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default.
• • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.9.8 Timer A, Channel 1 Interrupt Priority Level (TMRA1 IPL)—Bits 1–0 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.
Register Descriptions 5.6.10.3 Reload PWM A Interrupt Priority Level (PWMA_RL IPL)—Bits 11–10 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.10.4 Reload PWM B Interrupt Priority Level (PWMB_RL IPL)—Bits 9–8 This field is used to set the interrupt priority level for IRQs.
• • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.10.8 ADC B Conversion Complete Interrupt Priority Level (ADCB_CC IPL)—Bits 1–0 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.
Register Descriptions 5.6.12.2 Fast Interrupt 0 Vector Number (FAST INTERRUPT 0)—Bits 6–0 This value determines which IRQ will be a Fast Interrupt 0. Fast interrupts vector directly to a service routine based on values in the Fast Interrupt Vector Address registers without having to go to a jump table first; see Part 5.3.3. IRQs used as fast interrupts must be set to priority level 2. Unexpected results will occur if a fast interrupt vector is set to any other priority.
5.6.15 Fast Interrupt 1 Match Register (FIM1) Base + $E 15 14 13 12 11 10 9 8 7 Read 0 0 0 0 0 0 0 0 0 6 5 4 3 2 1 0 0 0 FAST INTERRUPT 1 Write RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 5-17 Fast Interrupt 1 Match Register (FIM1) 5.6.15.1 Reserved—Bits 15–7 This bit field is reserved or not implemented. It is read as 0, but cannot be modified by writing. 5.6.15.
Register Descriptions 5.6.17.2 Fast Interrupt 1 Vector Address High (FIVAH1)—Bits 4–0 The upper five bits of the vector address are used for Fast Interrupt 1. This register is combined with FIVAL1 to form the 21-bit vector address for Fast Interrupt 1 defined in the FIM1 register. 5.6.
5.6.20 IRQ Pending 2 Register (IRQP2) Base + $13 15 14 13 12 11 10 9 Read 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 PENDING [48:33] Write RESET 1 1 1 1 1 1 1 1 1 Figure 5-22 IRQ Pending 2 Register (IRQP2) 5.6.20.1 IRQ Pending (PENDING)—Bits 48–33 This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2 through 81. • • 0 = IRQ pending for this vector number 1 = No IRQ pending for this vector number 5.6.
Register Descriptions 5.6.22.1 IRQ Pending (PENDING)—Bits 80–65 This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2 through 81. • • 0 = IRQ pending for this vector number 1 = No IRQ pending for this vector number 5.6.
5.6.30 ITCN Control Register (ICTL) Base + $1D 15 Read INT 14 13 12 11 10 IPIC 9 8 7 6 5 VAB 4 3 2 1 0 1 IRQB STATE IRQA STATE IRQB EDG IRQA EDG 1 1 1 0 0 INT_DIS Write RESET 0 0 0 1 0 0 0 0 0 0 0 Figure 5-26 ITCN Control Register (ICTL) 5.6.30.1 Interrupt (INT)—Bit 15 This read-only bit reflects the state of the interrupt to the 56800E core. • • 0 = No interrupt is being sent to the 56800E core 1 = An interrupt is being sent to the 56800E core 5.6.30.
Resets 5.6.30.6 IRQB State Pin (IRQB STATE)—Bit 3 This read-only bit reflects the state of the external IRQB pin. 5.6.30.7 IRQA State Pin (IRQA STATE)—Bit 2 This read-only bit reflects the state of the external IRQA pin. 5.6.30.8 IRQB Edge Pin (IRQB Edg)—Bit 1 This bit controls whether the external IRQB interrupt is edge- or level-sensitive. During Stop and Wait modes, it is automatically level-sensitive.
Part 6 System Integration Module (SIM) 6.1 Introduction The SIM module is a system catchall for the glue logic that ties together the system-on-chip. It controls distribution of resets and clocks and provides a number of control features.
Operating Modes 6.3 Operating Modes Since the SIM is responsible for distributing clocks and resets across the chip, it must understand the various chip operating modes and take appropriate action. These are: • Reset Mode, which has two submodes: — POR and RESET operation The 56800E core and all peripherals are reset. This occurs when the internal POR is asserted or the RESET pin is asserted. — COP reset and software reset operation The 56800E core and all peripherals are reset.
6.5 Register Descriptions Table 6-1 SIM Registers (SIM_BASE = $00 F350) Address Offset Address Acronym Register Name Section Location Base + $0 SIM_CONTROL Control Register 6.5.1 Base + $1 SIM_RSTSTS Reset Status Register 6.5.2 Base + $2 SIM_SCR0 Software Control Register 0 6.5.3 Base + $3 SIM_SCR1 Software Control Register 1 6.5.3 Base + $4 SIM_SCR2 Software Control Register 2 6.5.3 Base + $5 SIM_SCR3 Software Control Register 3 6.5.
Register Descriptions Add.
6.5.1.3 Software Reset (SW RST)—Bit 4 This bit is always read as 0. Writing 1 to this field will cause the part to reset. 6.5.1.
Register Descriptions set the bit, while writing a 1 to the bit will clear it. 6.5.2.4 External Reset (EXTR)—Bit 3 If 1, the EXTR bit indicates an external system reset has occurred. This bit will be cleared by a Power-On Reset or by software. Writing a 0 to this bit position will set the bit, while writing a 1 to the bit position will clear it. Basically, when the EXTR bit is 1, the previous system reset was caused by the external RESET pin being asserted low. 6.5.2.
Base + $6 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 0 0 0 0 0 0 0 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 1 0 0 Write RESET Figure 6-6 Most Significant Half of JTAG ID (SIM_MSH_ID) 6.5.5 Least Significant Half of JTAG ID (SIM_LSH_ID) This read-only register displays the least significant half of the JTAG ID for the chip. This register reads $401D.
Register Descriptions 6.5.6.2 PWMA1—Bit 14 This bit controls the pull-up resistors on the FAULTA3 pin. 6.5.6.3 CAN—Bit 13 This bit controls the pull-up resistors on the CAN_RX pin. 6.5.6.4 EMI_MODE—Bit 12 This bit controls the pull-up resistors on the EMI_MODE pin. Note: 6.5.6.5 In this package, this input pin is double-bonded with the adjacent VSS pin and this bit should be changed to a 1 in order to reduce power consumption.
6.5.6.14 Reserved—Bit 2–0 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 6.5.7 CLKO Select Register (SIM_CLKOSR) The CLKO select register can be used to multiplex out any one of the clocks generated inside the clock generation and SIM modules. The default value is SYS_CLK. This path has been optimized in order to minimize any delay and clock duty cycle distortion.
Register Descriptions 6.5.7.6 • • Clockout Disable (CLKDIS)—Bit 5 0 = CLKOUT output is enabled and will output the signal indicated by CLKOSEL 1 = CLKOUT is tri-stated 6.5.7.7 CLockout Select (CLKOSEL)—Bits 4–0 Selects clock to be muxed out on the CLKO pin.
GPIOC_PER Register GPIO Controlled 0 I/O Pad Control 1 SIM_ GPS Register 0 Quad Timer Controlled 1 SPI Controlled Figure 6-10 Overall Control of Pads Using SIM_GPS Control Table 6-2 Control of Pads Using SIM_GPS Control 1 GPIOC_PER GPIOC_DTR SIM_GPS Quad Timer SCR Register OEN bits Control Registers GPIO Input 0 0 — — GPIO Output 0 1 — — Quad Timer Input / Quad Decoder Input 2 1 — 0 0 Quad Timer Output / Quad Decoder Input 3 1 — 0 1 SPI input 1 — 1 — SPI output 1 —
Register Descriptions Base + $B 15 14 13 12 11 10 9 8 7 6 5 4 Read 0 0 0 0 0 0 0 0 0 0 0 0 3 2 1 0 C3 C2 C1 C0 0 0 0 0 Write RESET 0 0 0 0 0 0 0 0 0 0 0 0 Figure 6-11 GPIO Peripheral Select Register (SIM_GPS) 6.5.8.1 Reserved—Bits 15–4 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 6.5.8.2 GPIOC3 (C3)—Bit 3 This bit selects the alternate function for GPIOC3.
Base + $C 15 14 13 12 11 10 9 8 TMRD TMRC 1 1 7 6 5 4 3 2 SCI1 SCI0 SPI1 SPI0 1 1 1 1 1 0 Read EMI ADCB ADCA CAN DEC1 DEC0 TMRB TMRA PWMB PWMA Write RESET 1 1 1 1 1 1 1 1 1 1 Figure 6-12 Peripheral Clock Enable Register (SIM_PCE) 6.5.9.1 External Memory Interface Enable (EMI)—Bit 15 Each bit controls clocks to the indicated peripheral. • • 1 = Clocks are enabled 0 = The clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.
Register Descriptions 6.5.9.7 Quad Timer D Enable (TMRD)—Bit 9 Each bit controls clocks to the indicated peripheral. • • 1 = Clocks are enabled 0 = The clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.8 Quad Timer C Enable (TMRC)—Bit 8 Each bit controls clocks to the indicated peripheral. • • 1 = Clocks are enabled 0 = The clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.
6.5.9.15 Pulse Width Modulator B Enable (PWMB)—Bit 1 Each bit controls clocks to the indicated peripheral. • • 1 = Clocks are enabled 0 = The clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.16 Pulse Width Modulator A Enable (PWMA)—Bit 0 Each bit controls clocks to the indicated peripheral. • • 1 = Clocks are enabled 0 = The clock is not provided to the peripheral (the peripheral is disabled) 6.5.
Clock Generation Overview Base + $D 15 14 13 12 11 10 9 8 7 6 5 4 3 2 Read 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 ISAL[23:22] Write 1 RESET 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Figure 6-14 I/O Short Address Location High Register (SIM_ISALH) 6.5.10.1 Input/Output Short Address Low (ISAL[23:22])—Bit 1–0 This field represents the upper two address bits of the “hard coded” I/O short address.
Table 6-3 Clock Operation in Power-Down Modes Mode Core Clocks Peripheral Clocks Description Run Active Active Device is fully functional Wait Core and memory clocks disabled Active Peripherals are active and can produce interrupts if they have not been masked off. Interrupts will cause the core to come out of its suspended state and resume normal operation. Typically used for power-conscious applications.
Resets Some applications require the 56800E STOP and WAIT instructions to be disabled. To disable those instructions, write to the SIM control register (SIM_CONTROL), described in Part 6.5.1. This procedure can be on either a permanent or temporary basis. Permanently assigned applications last only until their next reset. 6.9 Resets The SIM supports four sources of reset. The two asynchronous sources are the external RESET pin and the Power-On Reset (POR).
7.2 Flash Access Blocking Mechanisms The 56F8345/56F8145 have several operating functional and test modes. Effective Flash security must address operating mode selection and anticipate modes in which the on-chip Flash can be compromised and read without explicit user permission. Methods to block these are outlined in the next subsections. 7.2.1 Forced Operating Mode Selection At boot time, the SIM determines in which functional modes the device will operate.
Flash Access Blocking Mechanisms The LOCKOUT_RECOVERY instruction has an associated 7-bit Data Register (DR) that is used to control the clock divider circuit within the FM module. This divider, FM_CLKDIV[6:0], is used to control the period of the clock used for timed events in the FM erase algorithm. This register must be set with appropriate values before the lockout sequence can begin. Refer to the JTAG section of the 56F8300 Peripheral User Manual for more details on setting this register value.
EXAMPLE 1: If the system clock is the 8MHz crystal frequency because the PLL has not been set up, the input clock will be below 12.8MHz, so PRDIV8 = FM_CLKDIV[6] = 0. Using the following equation yields a DIV value of 19 for a clock of 200kHz, and a DIV value of 20 for a clock of 190kHz. This translates into an FM_CLKDIV[6:0] value of $13 or $14, respectively.
Introduction the backdoor key access. The customer would need to supply Technical Support with the backdoor key and the protocol to access the backdoor routine in the Flash. Additionally, the KEYEN bit that allows backdoor key access must be set. An alternative method for performing analysis on a secured hybrid controller would be to mass-erase and reprogram the Flash with the original code, but to modify the security bytes.
Table 8-1 56F8345 GPIO Ports Configuration GPIO Port Port Width Available Pins in 56F8345 C 11 11 4 pins - DEC1 / TMRB / SPI1 4 pins - DEC0 / TMRA 3 pins - PWMA current sense DEC1 / TMRB DEC0 / TMRA PWMA current sense D 13 11 2 pins - EMI CSn 4 pins - EMI CSn - Can only be used as GPIO 2 pins - SCI1 2 pins - EMI CSn - Not available in this package 3 pins - PWMB current sense EMI Chip Selects EMI Chip Selects SCI1 N/A PWMB current sense E 14 12 2 pins - SCI0 2 pins - EMI Address pins - Not av
Configuration Table 8-2 56F8145 GPIO Ports Configuration GPIO Port Port Width Available Pins in 56F8145 F 16 4 Peripheral Function Reset Function 4 pins - EMI Data - Can only be used as GPIO 12 pins - EMI Data - Not available in this package EMI Data N/A Table 8-3 GPIO External Signals Map Pins in shaded rows are not available in 56F8345 / 56F8145 Pins in italics are NOT available in the 56F8145 device GPIO Port GPIOA GPIO Bit Reset Function Functional Signal Package Pin # 0 Peripheral A8
Table 8-3 GPIO External Signals Map (Continued) Pins in shaded rows are not available in 56F8345 / 56F8145 Pins in italics are NOT available in the 56F8145 device GPIO Port GPIOB GPIOC GPIO Bit Reset Function Functional Signal Package Pin # 0 GPIO A161 27 1 GPIO A171 28 2 GPIO A181 29 3 GPIO A191 30 4 GPIO A20 / Prescaler_clock 31 5 N/A 6 N/A 7 N/A 0 Peripheral PHASEA1 / TB0 / SCLK12 9 1 Peripheral PHASEB1 / TB1 / MOSI12 10 2 Peripheral INDEX1 / TB2 / MISO12 11 3
Configuration Table 8-3 GPIO External Signals Map (Continued) Pins in shaded rows are not available in 56F8345 / 56F8145 Pins in italics are NOT available in the 56F8145 device GPIO Port GPIOD GPIO Bit Reset Function Functional Signal Package Pin # 0 GPIO CS21 42 1 GPIO CS31 43 2 GPIO CS41 44 3 GPIO CS51 45 4 GPIO CS61 46 5 GPIO CS71 47 6 Peripheral TXD1 40 7 Peripheral RXD1 41 8 N/A 9 N/A 10 Peripheral ISB0 48 11 Peripheral ISB1 50 12 Peripheral ISB2 51
Table 8-3 GPIO External Signals Map (Continued) Pins in shaded rows are not available in 56F8345 / 56F8145 Pins in italics are NOT available in the 56F8145 device GPIO Port GPIO Bit Reset Function Functional Signal Package Pin # 0 Peripheral TXD0 7 1 Peripheral RXD0 8 2 N/A 3 N/A 4 Peripheral SCLK0 124 5 Peripheral MOSI0 126 6 Peripheral MISO0 125 7 Peripheral SS0 123 8 Peripheral TC0 111 9 Peripheral TC1 113 10 Peripheral TD0 107 11 Peripheral TD1 108 12 Pe
JTAG Information Table 8-3 GPIO External Signals Map (Continued) Pins in shaded rows are not available in 56F8345 / 56F8145 Pins in italics are NOT available in the 56F8145 device GPIO Port GPIOF GPIO Bit Reset Function Functional Signal Package Pin # 0 Peripheral D71 22 1 Peripheral D81 23 2 Peripheral D91 24 3 Peripheral D101 26 4 N/A 5 N/A 6 N/A 7 N/A 8 N/A 9 N/A 10 N/A 11 N/A 12 N/A 13 N/A 14 N/A 15 N/A 1.
of devices designed for 3.3V and 5V power supplies. In such systems, a bus may carry both 3.3V- and 5V-compatible I/O voltage levels (a standard 3.3V I/O is designed to receive a maximum voltage of 3.3V ± 10% during normal operation without causing damage). This 5V-tolerant capability therefore offers the power savings of 3.3V I/O levels combined with the ability to receive 5V levels without damage.
General Characteristics Table 10-1 Absolute Maximum Ratings (Continued) (VSS = VSSA_ADC = 0) Characteristic Symbol Junction Temperature (Automotive) Junction Temperature (Industrial) Notes Min Max Unit TJ -40 150 °C TJ -40 125 °C Storage Temperature (Automotive) TSTG -55 150 °C Storage Temperature (Industrial) TSTG -55 150 °C 1. If corresponding GPIO pin is configured as open drain. Note: Pins in italics are NOT available in the 56F8145 device.
Table 10-2 56F8345/56F8145 ElectroStatic Discharge (ESD) Protection Characteristic Min Typ Max Unit ESD for Human Body Model (HBM) 2000 — — V ESD for Machine Model (MM) 200 — — V ESD for Charge Device Model (CDM) 500 — — V Table 10-3 Thermal Characteristics6 Value Characteristic Comments Symbol Unit Notes 128-pin LQFP Junction to ambient Natural convection Junction to ambient (@1m/sec) RθJA 50.8 °C/W 2 RθJMA 46.
General Characteristics 7. TJ = Junction temperature TA = Ambient temperature Note: The 56F8145 device is guaranteed to 40MHz and specified to meet Industrial requirements only; CAN is NOT available on the 56F8145 device. Table 10-4 Recommended Operating Conditions (VREFLO = 0V, VSS = VSSA_ADC = 0V, VDDA = VDDA_ADC = VDDA_OSC_PLL ) Characteristic Supply voltage ADC Supply Voltage Oscillator / PLL Supply Voltage Symbol Notes VDD_IO VDDA_ADC, VREFH VREFH must be less Min Typ Max Unit 3 3.3 3.
10.2 DC Electrical Characteristics Note: The 56F8145 device is specified to meet Industrial requirements only; CAN is NOT available on the 56F8145 device. Table 10-5 DC Electrical Characteristics At Recommended Operating Conditions; see Table 10-4 Characteristic Symbol Notes Min Typ Max Unit Test Conditions Output High Voltage VOH 2.4 — — V IOH = IOHmax Output Low Voltage VOL — — 0.4 V IOL = IOLmax IIH Pin Groups 1, 2, 5, 6, 9 — 0 +/- 2.5 μA VIN = 3.0V to 5.
DC Electrical Characteristics Table 10-6 Power-On Reset Low Voltage Parameters Characteristic Symbol Min Typ Max Units POR Trip Point POR 1.75 1.8 1.9 V LVI, 2.5 volt Supply, trip point1 VEI2.5 — 2.14 — V LVI, 3.3 volt supply, trip point2 VEI3.3 — 2.7 — V Bias Current I bias — 110 130 μA 1. When VDD_CORE drops below VEI2.5, an interrupt is generated. 2. When VDD_CORE drops below VEI3.3, an interrupt is generated.
Table 10-8 Current Consumption per Power Supply Pin (Typical) On-Chip Regulator Disabled (OCR_DIS = High) Mode RUN1_MAC IDD_Core IDD_IO1 IDD_ADC IDD_OSC_PLL 150mA 13μA 50mA 2.5mA Test Conditions • 60MHz Device Clock • All peripheral clocks are enabled • All peripherals running • Continuous MAC instructions with fetches from Data RAM • ADC powered on and clocked Wait3 86mA 13μA 65μA 2.
DC Electrical Characteristics Table 10-10. PLL Parameters Characteristics Symbol Min Typical Max Unit PLL Start-up time TPS 0.3 0.5 10 ms Resonator Start-up time TRS 0.1 0.18 1 ms Min-Max Period Variation TPV 120 — 200 ps Peak-to-Peak Jitter TPJ — — 175 ps Bias Current IBIAS — 1.5 2 mA IPD — 100 150 μA Quiescent Current, power-down mode 10.2.1 Temperature Sense Note: Temperature Sensor is NOT available in the 56F8145 device.
10.3 AC Electrical Characteristics Tests are conducted using the input levels specified in Table 10-5. Unless otherwise specified, propagation delays are measured from the 50% to the 50% point, and rise and fall times are measured between the 10% and 90% points, as shown in Figure 10-1. Low VIH Input Signal High 90% 50% 10% Midpoint1 VIL Fall Time Rise Time Note: The midpoint is VIL + (VIH – VIL)/2.
External Clock Operation Timing 10.5 External Clock Operation Timing Table 10-13 External Clock Operation Timing Requirements1 Characteristic Symbol Min Typ Max Unit Frequency of operation (external clock driver)2 fosc 0 — 120 MHz Clock Pulse Width3 tPW 3.0 — — ns External clock input rise time4 trise — — 10 ns External clock input fall time5 tfall — — 10 ns 1. Parameters listed are guaranteed by design. 2.
3. This is the minimum time required after the PLL set up is changed to ensure reliable operation. 10.7 Crystal Oscillator Timing Table 10-15 Crystal Oscillator Parameters Characteristic Symbol Min Typ Max Unit Crystal Start-up time TCS 4 5 10 ms Resonator Start-up time TRS 0.1 0.18 1 ms RESR — — 120 ohms Crystal Peak-to-Peak Jitter TD 70 — 250 ps Crystal Min-Max Period Variation TPV 0.12 — 1.
Reset, Stop, Wait, Mode Select, and Interrupt Timing 3. The interrupt instruction fetch is visible on the pins only in Mode 3.
tIW IRQA tIF A0–A15 First Instruction Fetch Not IRQA Interrupt Vector Figure 10-8 Recovery from Stop State Using Asynchronous Interrupt Timing 10.9 Serial Peripheral Interface (SPI) Timing Table 10-17 SPI Timing1 Characteristic Symbol Cycle time Master Slave Min Max Unit 50 50 — — ns ns — 25 — — ns ns — 100 — — ns ns 17.6 25 — — ns ns 24.1 25 — — ns ns 20 0 — — ns ns 0 2 — — ns ns 4.8 15 ns 3.7 15.2 ns — — 4.5 20.
Serial Peripheral Interface (SPI) Timing Table 10-17 SPI Timing1 (Continued) Characteristic Symbol Data invalid Master Slave tDI Rise time Master Slave tR Fall time Master Slave tF Min Max Unit 0 0 — — ns ns — — 11.5 10.0 ns ns — — 9.7 9.0 ns ns See Figure 10-9, 10-10, 10-11 10-9, 10-10, 10-11, 10-12 10-9, 10-10, 10-11, 10-12 1. Parameters listed are guaranteed by design.
SS (Input) SS is held High on master tC tF tR tCL SCLK (CPOL = 0) (Output) tCH tF tCL SCLK (CPOL = 1) (Output) tCH tDS tR MISO (Input) MSB in Bits 14–1 tDI tDV(ref) MOSI (Output) tDH Master MSB out tDV Bits 14– 1 tF LSB in tDI(ref) Master LSB out tR Figure 10-10 SPI Master Timing (CPHA = 1) 56F8345 Technical Data, Rev.
Serial Peripheral Interface (SPI) Timing SS (Input) tC tF tCL SCLK (CPOL = 0) (Input) tELG tR tCH tELD tCL SCLK (CPOL = 1) (Input) tCH tA MISO (Output) Slave MSB out tF tR Bits 14–1 tDS Slave LSB out tDV tDI tDH MOSI (Input) MSB in tD Bits 14–1 tDI LSB in Figure 10-11 SPI Slave Timing (CPHA = 0) SS (Input) tF tC tR tCL SCLK (CPOL = 0) (Input) tCH tELG tELD tCL SCLK (CPOL = 1) (Input) tDV tCH tR tA MISO (Output) Slave MSB out Bits 14–1 tDS tDV tDH MOSI (Input) tD
10.10 Quad Timer Timing Table 10-18 Timer Timing1, 2 Characteristic Symbol Min Max Unit See Figure PIN 2T + 6 — ns 10-13 Timer input high / low period PINHL 1T + 3 — ns 10-13 Timer output period POUT 1T - 3 — ns 10-13 POUTHL 0.5T - 3 — ns 10-13 Timer input period Timer output high / low period 1. In the formulas listed, T = the clock cycle. For 60MHz operation, T = 16.67ns. 2. Parameters listed are guaranteed by design.
Serial Communication Interface (SCI) Timing PPH PPH PPH PPH Phase A (Input) PHL PIN PHL Phase B PHL (Input) PIN PHL Figure 10-14 Quadrature Decoder Timing 10.12 Serial Communication Interface (SCI) Timing Table 10-20 SCI Timing1 Characteristic Symbol Min Max Unit See Figure BR — (fMAX/16) Mbps — RXD3 Pulse Width RXDPW 0.965/BR 1.04/BR ns 10-15 TXD4 Pulse Width TXDPW 0.965/BR 1.04/BR ns 10-16 Baud Rate2 1. Parameters listed are guaranteed by design. 2.
TXD SCI receive data pin (Input) TXDPW Figure 10-16 TXD Pulse Width 10.13 Controller Area Network (CAN) Timing Note: CAN is NOT available in the 56F8145 device. Table 10-21 CAN Timing1 Characteristic Baud Rate Bus Wake Up detection Symbol Min Max Unit See Figure BRCAN — 1 Mbps — T WAKEUP 5 — μs 10-17 1. Parameters listed are guaranteed by design CAN_RX CAN receive data pin (Input) T WAKEUP Figure 10-17 Bus Wake Up Detection 10.
JTAG Timing Table 10-22 JTAG Timing Characteristic Symbol Min Max Unit See Figure TCK low to TDO data valid tDV — 30 ns 10-19 TCK low to TDO tri-state tTS — 30 ns 10-19 tTRST 2T2 — ns 10-20 TRST assertion time 1. TCK frequency of operation must be less than 1/8 the processor rate. 2.
TRST (Input) tTRST Figure 10-20 TRST Timing Diagram 10.15 Analog-to-Digital Converter (ADC) Parameters Table 10-23 ADC Parameters Characteristic Symbol Min Typ Max Unit VADIN VREFL — VREFH V Resolution RES 12 — 12 Bits Integral Non-Linearity1 INL — +/- 2.4 +/- 3.2 LSB2 Differential Non-Linearity DNL — +/- 0.7 < +1 LSB2 Input voltages Monotonicity GUARANTEED ADC internal clock fADIC 0.
Analog-to-Digital Converter (ADC) Parameters Table 10-23 ADC Parameters (Continued) Characteristic Symbol Min Typ Max Unit Uncalibrated Offset Voltage VOFFSET — +/- 18 +/- 46 mV Calibrated Absolute Error6 AECAL — See Figure 10-21 — LSBs Calibration Factor 17 CF1 — -0.003141 — — Calibration Factor 27 CF2 — -17.6 — — — — -60 — dB Vcommon — (VREFH - VREFLO) / 2 — V SNR — 64.6 — db SINAD — 59.1 — db THD — 60.6 — db Spurious Free Dynamic Range SFDR — 61.
Figure 10-21 ADC Absolute Error Over Processing and Temperature Extremes Before and After Calibration for VDCin = 0.60V and 2.70V Note: The absolute error data shown in the graphs above reflects the effects of both gain error and offset error. The data was taken on 15 parts: three each from four processing corner lots as well as three from one nominally processed lot, each at three temperatures: -40°C, 27°C, and 150°C (giving the 45 data points shown above), for two input DC voltages: 0.60V and 2.70V.
Equivalent Circuit for ADC Inputs 10.16 Equivalent Circuit for ADC Inputs Figure 10-22 illustrates the ADC input circuit during sample and hold. S1 and S2 are always open/closed at the same time that S3 is closed/open. When S1/S2 are closed & S3 is open, one input of the sample and hold circuit moves to VREFH - VREFH / 2, while the other charges to the analog input voltage.
3 Analog Input 4 S1 (VREFH - VREFLO) / 2 1 1. 2. 3. 4. C1 S2 2 S/H S3 C2 C1 = C2 = 1pF Parasitic capacitance due to package, pin-to-pin and pin-to-package base coupling; 1.8pf Parasitic capacitance due to the chip bond pad, ESD protection devices and signal routing; 2.04pf Equivalent resistance for the ESD isolation resistor and the channel select mux; 500 ohms Sampling capacitor at the sample and hold circuit.
Power Consumption Table 10-24 IO Loading Coefficients at 10MHz Intercept Slope PDU08DGZ_ME 1.3 0.11mW / pF PDU04DGZ_ME 1.15mW 0.11mW / pF Power due to capacitive loading on output pins is (first order) a function of the capacitive load and frequency at which the outputs change. Table 10-24 provides coefficients for calculating power dissipated in the IO cells as a function of capacitive load.
Part 11 Packaging 11.1 56F8345 Package and Pin-Out Information This section contains package and pin-out information for the 56F8345. This device comes in a 128-pin Low-profile Quad Flat Pack (LQFP). Figure 11-1. shows the package outline for the 128-pin LQFP, Figure 11-3 shows the mechanical parameters for this package, and Table 11-1 lists the pin-out for the 128-pin LQFP. Please see freescale.
PHASEB0 PHASEA0 MOSI0 MISO0 SCLK0 SS0 VCAP2 CAN_RX CAN_TX VPP1 TDO TDI TMS TCK TRST TC1 VDD_IO TC0 TD3 TD2 TD1 TD0 ISA2 ISA1 ISA0 ANB7 56F8345 Package and Pin-Out Information INDEX0 HOME0 VSS VDD_IO Orientation Mark 103 PIN 1 VPP2 CLKO TXD0 RXD0 PHASEA1 PHASEB1 INDEX1 HOME1 VCAP4 VDD_IO GPIOA0 GPIOA1 GPIOA2 GPIOA3 GPIOA4 GPIOA5 VSS GPIOF0 GPIOF1 GPIOF2 VDD_IO 65 39 PWMB5 TXD1 RXD1 GPIOD0 GPIOD1 GPIOD2 GPIOD3 GPIOD4 GPIOD5 ISB0 VCAP1 ISB1 ISB2 IRQA IRQB FAULTB0 FAULTB1 FAULTB2 FAULTB3 PWMA0 VSS PWMA1
Table 11-1 56F8345 128-Pin LQFP Package Identification by Pin Number (Continued) Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name Pin No.
56F8145 Package and Pin-Out Information Table 11-1 56F8345 128-Pin LQFP Package Identification by Pin Number (Continued) Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name 32 PWMB0 64 PWMA4 96 ANB0 128 PHASEB0 11.2 56F8145 Package and Pin-Out Information This section contains package and pin-out information for the 56F8145. This device comes in a 128-pin Low-profile Quad Flat Pack (LQFP). Figure 11-1.
PHASEB0 PHASEA0 MOSI0 MISO0 SCLK0 SS0 VCAP2 NC NC VPP1 TDO TDI TMS TCK TRST TC1 VDD_IO TC0 GPIOE13 GPIOE12 GPIOE11 GPIOE10 GPIOC10 GPIOC9 GPIOC8 ANB7 INDEX0 HOME0 VSS VDD_IO Orientation Mark PIN 1 103 VPP2 CLKO TXD0 RXD0 SCLK1 MOSI1 MISO1 SS1 VCAP4 VDD_IO GPIOA0 GPIOA1 GPIOA2 GPIOA3 GPIOA4 GPIOA5 VSS GPIOF0 GPIOF1 GPIOF2 VDD_IO 65 39 PWMB5 TXD1 RXD1 GPIOD0 GPIOD1 GPIOD2 GPIOD3 GPIOD4 GPIOD5 ISB0 VCAP1 ISB1 ISB2 IRQA IRQB FAULTB0 FAULTB1 FAULTB2 FAULTB3 NC VSS NC NC VDD_IO NC NC GPIOF3 GPIOB0 GPIOB1 G
56F8145 Package and Pin-Out Information Table 11-2 56F8145 128-Pin LQFP Package Identification by Pin Number Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name Pin No.
Table 11-2 56F8145 128-Pin LQFP Package Identification by Pin Number (Continued) Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name 26 GPIOF31 58 NC 90 VREFN 122 VCAP2 27 GPIOB0 59 VSS 91 VREFMID 123 SS0 28 GPIOB1 60 NC 92 VREFP 124 SCLK0 29 GPIOB2 61 NC 93 VREFH 125 MISO0 30 GPIOB3 62 VDD_IO 94 VDDA_ADC 126 MOSI0 31 GPIOB4 63 NC 95 VSSA_ADC 127 PHASEA0 32 PWMB0 64 NC 96 ANB0 128 PHASEB0 56F8345 Technical Data, Rev.
56F8145 Package and Pin-Out Information DIM NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE H IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS A, B, AND D TO BE DETERMINED AT DATUM PLANE H. 5. DIMENSIONS D AND E TO BE DETERMINED AT SEATING PLANE C. 6. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 PER SIDE.
Please see www.freescale.com for the most current case outline. 56F8345 Technical Data, Rev.
Thermal Design Considerations Part 12 Design Considerations 12.1 Thermal Design Considerations An estimation of the chip junction temperature, TJ, can be obtained from the equation: TJ = TA + (RθJΑ x PD) where: TA = Ambient temperature for the package (oC) RθJΑ = Junction-to-ambient thermal resistance (oC/W) PD = Power dissipation in the package (W) The junction-to-ambient thermal resistance is an industry-standard value that provides a quick and easy estimation of thermal performance.
The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and over about 1mm of wire extending from the junction.
Power Distribution and I/O Ring Implementation • • Because the device’s output signals have fast rise and fall times, PCB trace lengths should be minimal Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance. This is especially critical in systems with higher capacitive loads that could create higher transient currents in the VDD and VSS circuits.
Part 13 Ordering Information Table 13-1 lists the pertinent information needed to place an order. Consult a Freescale Semiconductor sales office or authorized distributor to determine availability and to order parts. Table 13-1 Ordering Information Part Supply Voltage Package Type Pin Count Frequency (MHz) Ambient Temperature Range Order Number MC56F8345 3.0–3.6 V Low-Profile Quad Flat Pack (LQFP) 128 60 -40° to + 105° C MC56F8345VFG60 MC56F8345 3.0–3.
Power Distribution and I/O Ring Implementation THIS PAGE IS INTENTIONALLY BLANK 56F8345 Technical Data, Rev.
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