Datasheet

JTAG Information
56F8345 Technical Data, Rev. 17
Freescale Semiconductor 131
Preliminary
Part 9 Joint Test Action Group (JTAG)
9.1 JTAG Information
Please contact your Freescale marketing representative or authorized distributor for
device/package-specific BSDL information.
Part 10 Specifications
10.1 General Characteristics
The 56F8345/56F8145 are fabricated in high-density CMOS with 5V-tolerant TTL-compatible digital
inputs. The term “5V-tolerant” refers to the capability of an I/O pin, built on a 3.3V-compatible process
technology, to withstand a voltage up to 5.5V without damaging the device. Many systems have a mixture
GPIOF
0Peripheral
D7
1
22
1Peripheral
D8
1
23
2Peripheral
D9
1
24
3Peripheral
D10
1
26
4
N/A
5 N/A
6 N/A
7 N/A
8 N/A
9 N/A
10 N/A
11 N/A
12 N/A
13 N/A
14 N/A
15 N/A
1. Not useful in reset configuration in this package - reconfigure as GPIO
2. See Part 6.5.8 to determine how to select peripherals from this set; DEC1 is the selected peripheral at reset
Table 8-3 GPIO External Signals Map (Continued)
Pins in shaded rows are not available in 56F8345 / 56F8145
Pins in italics are NOT available in the 56F8145 device
GPIO Port GPIO Bit
Reset Function
Functional Signal Package Pin #