Datasheet

Reset, Stop, Wait, Mode Select, and Interrupt Timing
56F8345 Technical Data, Rev. 17
Freescale Semiconductor 143
Preliminary
Figure 10-4 Asynchronous Reset Timing
Figure 10-5 External Interrupt Timing (Negative Edge-Sensitive)
Figure 10-6 External Level-Sensitive Interrupt Timing
Figure 10-7 Interrupt from Wait State Timing
3. The interrupt instruction fetch is visible on the pins only in Mode 3.
First Fetch
t
RA
t
RAZ
t
RDA
A0–A15,
D0–D15
RESET
IRQA,
IRQB
t
IRW
t
IDM
A0–A15
IRQA,
IRQB
First Interrupt Instruction Execution
a) First Interrupt Instruction Execution
t
IG
General
Purpose
I/O Pin
IRQA,
IRQB
b) General Purpose I/O
Instruction Fetch
t
IRI
IRQA,
IRQB
First Interrupt Vector
A0–A15