Datasheet

Serial Peripheral Interface (SPI) Timing
56F8345 Technical Data, Rev. 17
Freescale Semiconductor 145
Preliminary
Figure 10-9 SPI Master Timing (CPHA = 0)
Data invalid
Master
Slave
t
DI
0
0
—
—
ns
ns
10-9, 10-10,
10-11
Rise time
Master
Slave
t
R
—
—
11.5
10.0
ns
ns
10-9, 10-10,
10-11, 10-12
Fall time
Master
Slave
t
F
—
—
9.7
9.0
ns
ns
10-9, 10-10,
10-11, 10-12
1. Parameters listed are guaranteed by design.
Table 10-17 SPI Timing
1
(Continued)
Characteristic Symbol Min Max Unit See Figure
SCLK (CPOL = 0)
(Output)
SCLK (CPOL = 1)
(Output)
MISO
(Input)
MOSI
(Output)
MSB in Bits 14–1 LSB in
t
F
t
C
t
CL
t
CL
t
R
t
R
t
F
t
DS
t
DH
t
CH
t
DI
t
DV
t
DI
(ref)
t
R
Master MSB out Bits 14–1 Master LSB out
SS
(Input)
t
CH
SS is held High on master
t
F