Datasheet

JTAG Timing
56F8345 Technical Data, Rev. 17
Freescale Semiconductor 151
Preliminary
Figure 10-18 Test Clock Input Timing Diagram
Figure 10-19 Test Access Port Timing Diagram
TCK low to TDO data valid
t
DV
—30ns 10-19
TCK low to TDO tri-state
t
TS
—30ns 10-19
TRST
assertion time
t
TRST
2T
2
—ns 10-20
1. TCK frequency of operation must be less than 1/8 the processor rate.
2. T = processor clock period (nominally 1/60MHz)
Table 10-22 JTAG Timing
Characteristic Symbol Min Max Unit See Figure
TCK
(Input)
V
M
V
IL
V
M
= V
IL
+ (V
IH
– V
IL
)/2
t
PW
1/f
OP
t
PW
V
M
V
IH
Input Data Valid
Output Data Valid
Output Data Valid
t
DS
t
DH
t
DV
t
TS
t
DV
TCK
(Input)
TDI
(Input)
TDO
(Output)
TDO
(Output
)
TDO
(Output)
TMS