Datasheet

Analog-to-Digital Converter (ADC) Parameters
56F8345 Technical Data, Rev. 17
Freescale Semiconductor 153
Preliminary
Uncalibrated Offset Voltage
V
OFFSET
— +/- 18 +/- 46 mV
Calibrated Absolute Error
6
AE
CAL
— See Figure 10-21 —LSBs
Calibration Factor 1
7
CF1 — -0.003141 — —
Calibration Factor 2
7
CF2 — -17.6 — —
Crosstalk between channels
—— -60 —dB
Common Mode Voltage
V
common
—(V
REFH
- V
REFLO
) / 2 — V
Signal-to-noise ratio
SNR — 64.6 — db
Signal-to-noise plus distortion ratio
SINAD — 59.1 — db
Total Harmonic Distortion
THD — 60.6 — db
Spurious Free Dynamic Range
SFDR — 61.1 — db
Effective Number Of Bits
8
ENOB — 9.6 — Bits
1. INL measured from V
in
= .1V
REFH
to V
in
= .9V
REFH
10% to 90% Input Signal Range
2. LSB = Least Significant Bit
3. ADC clock cycles
4. Assumes each voltage reference pin is bypassed with 0.1μF ceramic capacitors to ground
5. The current that can be injected or sourced from an unselected ADC signal input without impacting the performance of
the ADC. This allows the ADC to operate in noisy industrial environments where inductive flyback is possible.
6. Absolute error includes the effects of both gain error and offset error.
7. Please see the 56F8300 Peripheral User’s Manual for additional information on ADC calibration.
8. ENOB = (SINAD - 1.76)/6.02
Table 10-23 ADC Parameters (Continued)
Characteristic Symbol Min Typ Max Unit