Datasheet

Introduction
56F8345 Technical Data, Rev. 17
Freescale Semiconductor 17
Preliminary
Part 2 Signal/Connection Descriptions
2.1 Introduction
The input and output signals of the 56F8345 and 56F8145 are organized into functional groups, as detailed
in Table 2-1 and as illustrated in Figure 2-1. In Table 2-2, each table row describes the signal or signals
present on a pin.
Table 2-1 Functional Group Pin Allocations
Functional Group
Number of Pins in Package
56F8345 56F8145
Power (V
DD
or V
DDA
)
99
Power Option Control
11
Ground (V
SS
or V
SSA
)
66
Supply Capacitors
1
& V
PP
1. If the on-chip regulator is disabled, the V
CAP
pins serve as 2.5V V
DD_CORE
power inputs
66
PLL and Clock
44
Bus Control
66
Interrupt and Program Control
44
Pulse Width Modulator (PWM) Ports
26 13
Serial Peripheral Interface (SPI) Port 0
44
Serial Peripheral Interface (SPI) Port 1
—4
Quadrature Decoder Port 0
2
2. Alternately, can function as Quad Timer pins or GPIO
44
Quadrature Decoder Port 1
3
3. Pins in this section can function as Quad Timer, SPI 1, orGPIO
4—
Serial Communications Interface (SCI) Ports
44
CAN Ports
2—
Analog-to-Digital Converter (ADC) Ports
21 21
Timer Module Ports
64
JTAG/Enhanced On-Chip Emulation (EOnCE)
55
Temperature Sense
1—
Dedicated GPIO ( Address Bus = 11; Data Bus = 4
4
)
4. EMI not functional in these packages; use as GPIO pins.
Note: See Table 1-1 for 56F8145 functional differences.
28 28