Datasheet

Peripheral Memory Mapped Registers

56F8345 Technical Data, Rev. 17

Freescale Semiconductor 49

Preliminary

Table 4-10 External Memory Integration Registers Address Map

(EMI_BASE = $00 F020)

Acronym

Address

Offset

CSBAR 0 $0 Chip Select Base Address Register 0 0 x 0004 = 64K since

EXTBOOT = EMI_MODE

= 0

This table added to provide complete information, but this peripheral

is not functional in the 56F8345/56F8145 package

CSBAR 1 $1 Chip Select Base Address Register 1 0 x 0004 = 64K since

EMI_MODE = 0

CSBAR 2 $2 Chip Select Base Address Register 2

CSBAR 3 $3 Chip Select Base Address Register 3

CSBAR 4 $4 Chip Select Base Address Register 4

CSBAR 5 $5 Chip Select Base Address Register 5

CSBAR 6 $6 Chip Select Base Address Register 6

CSBAR 7 $7 Chip Select Base Address Register 7

CSOR 0 $8 Chip Select Option Register 0

CSOR 1 $9 Chip Select Option Register 1

CSOR 2 $A Chip Select Option Register 2

CSOR 3 $B Chip Select Option Register 3

CSOR 4 $C Chip Select Option Register 4

CSOR 5 $D Chip Select Option Register 5

CSOR 6 $E Chip Select Option Register 6

CSOR 7 $F Chip Select Option Register 7

CSTC 0 $10 Chip Select Timing Control Register 0

CSTC 1 $11 Chip Select Timing Control Register 1

CSTC 2 $12 Chip Select Timing Control Register 2

CSTC 3 $13 Chip Select Timing Control Register 3

CSTC 4 $14 Chip Select Timing Control Register 4

CSTC 5 $15 Chip Select Timing Control Register 5

CSTC 6 $16 Chip Select Timing Control Register 6

CSTC 7 $17 Chip Select Timing Control Register 7

BCR $18 Bus Control Register

Table 4-11 Quad Timer A Registers Address Map

(TMRA_BASE = $00 F040)

TMRA0_CMP1 $0 Compare Register 1