Datasheet

Peripheral Memory Mapped Registers

56F8345 Technical Data, Rev. 17

Freescale Semiconductor 63

Preliminary

Table 4-23 Serial Communication Interface 0 Registers Address Map

(SCI0_BASE = $00 F280)

SCI0_SCIBR $0 Baud Rate Register

SCI0_SCICR $1 Control Register

Reserved

SCI0_SCISR $3 Status Register

SCI0_SCIDR $4 Data Register

Table 4-24 Serial Communication Interface 1 Registers Address Map

(SCI1_BASE = $00 F290)

SCI1_SCIBR $0 Baud Rate Register

SCI1_SCICR $1 Control Register

Reserved

SCI1_SCISR $3 Status Register

SCI1_SCIDR $4 Data Register

Table 4-25 Serial Peripheral Interface 0 Registers Address Map

(SPI0_BASE = $00 F2A0)

SPI0_SPSCR $0 Status and Control Register

SPI0_SPDSR $1 Data Size Register

SPI0_SPDRR $2 Data Receive Register

SPI0_SPDTR $3 Data Transmitter Register

Table 4-26 Serial Peripheral Interface 1 Registers Address Map

(SPI1_BASE = $00 F2B0)

SPI1_SPSCR $0 Status and Control Register

SPI1_SPDSR $1 Data Size Register

SPI1_SPDRR $2 Data Receive Register