Datasheet

Peripheral Memory Mapped Registers

56F8345 Technical Data, Rev. 17

Freescale Semiconductor 67

Preliminary

Table 4-34 GPIOF Registers Address Map

(GPIOF_BASE = $00 F340)

GPIOF_PUR $0 Pull-up Enable Register 0 x FFFF

GPIOF_DR $1 Data Register 0 x 0000

GPIOF_DDR $2 Data Direction Register 0 x 0000

GPIOF_PER $3 Peripheral Enable Register 0 x FFFF

GPIOF_IAR $4 Interrupt Assert Register 0 x 0000

GPIOF_IENR $5 Interrupt Enable Register 0 x 0000

GPIOF_IPOLR $6 Interrupt Polarity Register 0 x 0000

GPIOF_IPR $7 Interrupt Pending Register 0 x 0000

GPIOF_IESR $8 Interrupt Edge-Sensitive Register 0 x 0000

GPIOF_PPMODE $9 Push-Pull Mode Register 0 x FFFF

GPIOF_RAWDATA $A Raw Data Input Register —

Table 4-35 System Integration Module Registers Address Map

(SIM_BASE = $00 F350)

SIM_CONTROL $0 Control Register

SIM_RSTSTS $1 Reset Status Register

SIM_SCR0 $2 Software Control Register 0

SIM_SCR1 $3 Software Control Register 1

SIM_SCR2 $4 Software Control Register 2

SIM_SCR3 $5 Software Control Register 3

SIM_MSH_ID $6 Most Significant Half JTAG ID

SIM_LSH_ID $7 Least Significant Half JTAG ID

SIM_PUDR $8 Pull-up Disable Register

Reserved

SIM_CLKOSR $A Clock Out Select Register

SIM_GPS $B Quad Decoder 1 / Timer B / SPI 1 Select Register

SIM_PCE $C Peripheral Clock Enable Register

SIM_ISALH $D I/O Short Address Location High Register

SIM_ISALL $E I/O Short Address Location Low Register