56F8346/56F8146 Data Sheet Preliminary Technical Data 56F8300 16-bit Digital Signal Controllers MC56F8346 Rev. 15 01/2007 freescale.
Document Revision History Version History Description of Change Rev 1.0 Pre-Release version, Alpha customers only Rev 2.0 Initial Public Release Rev 3.0 Corrected typo in Table 10-4, Flash Endurance is 10,000 cycles. Addressed additional grammar issues. Rev 4.0 Added “Typical Min” values to Table 10-16. Edited grammar, spelling, consistency of language throughout family.
Document Revision History (Continued) Version History Rev 14.0 Rev. 15 Description of Change Replaced “Tri-stated” with an explanation in State During Reset column in Table 2-2 • Added the following note to the description of the TMS signal in Table 2-2: Note: Always tie the TMS pin to VDD through a 2.2K resistor. • Added the following note to the description of the TRST signal in Table 2-2: Note: For normal operation, connect TRST directly to VSS.
56F8346 Technical Data, Rev.
6F8346/56F8146 General Description Note: Features in italics are NOT available in the 56F8146 device.
Table of Contents Part 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1 1.2 1.3 1.4 1.5 1.6 56F8346/56F8146 Features . . . . . . . . . . . .7 Device Description. . . . . . . . . . . . . . . . . . . .9 Award-Winning Development Environment . . . . . . . . . . . . . . . . . . .11 Architecture Block Diagram . . . . . . . . . . . .11 Product Documentation . . . . . . . . . . . . . . .15 Data Sheet Conventions . . . . . . . . . . . . . .16 Part 2 Signal/Connection Descriptions . . . . 17 2.1 2.
56F8346/56F8146 Features Part 1 Overview 1.1 56F8346/56F8146 Features 1.1.1 • • • • • • • • • • • • • • 1.1.
1.1.3 Memory Note: Features in italics are NOT available in the 56F8146 device.
Device Description • • Two Serial Communication Interfaces (SCIs), each with two pins (or four additional GPIO lines) Up to two Serial Peripheral Interfaces (SPIs), both with configurable 4-pin port (or eight additional GPIO lines) — In the 56F8346, SPI1 can also be used as Quadrature Decoder 1 or Quad Timer B — In the 56F8146, SPI1 can alternately be used only as GPIO • • • • • • • • 1.1.
1.2.1 56F8346 Features The 56F8346 controller includes 128KB of Program Flash and 8KB of Data Flash (each programmable through the JTAG port) with 4KB of Program RAM and 8KB of Data RAM. It also supports program execution from external memory. A total of 8KB of Boot Flash is incorporated for easy customer inclusion of field-programmable software routines that can be used to program the main Program and Data Flash memory areas.
Award-Winning Development Environment A key application-specific feature of the 56F8146 is the inclusion of one Pulse Width Modulator (PWM) module. This module incorporates three complementary, individually programmable PWM signal output pairs and can also support six independent PWM functions to enhance motor control functionality. Complementary operation permits programmable dead time insertion, distortion correction via current sensing by software, and separate top and bottom output polarity control.
Also shown in Figure 1-2 are connections between the PWM, Timer C and ADC blocks. These connections allow the PWM and/or Timer C to control the timing of the start of ADC conversions. The Timer C channel indicated can generate periodic start (SYNC) signals to the ADC to start its conversions. In another operating mode, the PWM load interrupt (SYNC output) signal is routed internally to the Timer C input channel as indicated.
Architecture Block Diagram 5 JTAG / EOnCE Boot Flash pdb_m[15:0] pab[20:0] Program Flash cdbw[13:0] Program RAM 56800E EMI CHIP TAP Controller TAP Linking Module External JTAG Port 17 16 6 xab1[23:0] xab2[23:0] Address Data Control Data RAM Data Flash cdbr_m[31:0] xdb2_m[15:0] IPBus Bridge To Flash Control Logic Flash Interface Units NOT available on the 56F8146 device. IPBus Figure 1-1 System Bus Interfaces Note: Flash memories are encapsulated within the Flash Interface Unit (FIU).
To/From IPBus Bridge Interrupt Controller CLKGEN (OSC/PLL) Low-Voltage Interrupt Timer A POR & LVI 4 System POR Quadrature Decoder 0 SIM 2 RESET Timer D COP Reset Timer B 4 COP 2 FlexCAN Quadrature Decoder 1 SPI 1 12 PWMA SYNC Output GPIOA 13 PWMB GPIOB SYNC Output GPIOC ch3i ch2i 1 Timer C GPIOD ch2i ch3i GPIOE 8 GPIOF 4 2 ADCB SPI0 SCI0 TEMP_SENSE 2 8 ADCA 1 SCI1 NOT available on the 56F8146 device.
Product Documentation Table 1-2 Bus Signal Names Name Function Program Memory Interface pdb_m[15:0] Program data bus for instruction word fetches or read operations. cdbw[15:0] Primary core data bus used for program memory writes. (Only these 16 bits of the cdbw[31:0] bus are used for writes to program memory.) pab[20:0] Program memory address bus. Data is returned on pdb_m bus. Primary Data Memory Interface Bus cdbr_m[31:0] Primary core data bus for memory reads. Addressed via xab1 bus.
1.6 Data Sheet Conventions This data sheet uses the following conventions: OVERBAR This is used to indicate a signal that is active when pulled low. For example, the RESET pin is active when low. “asserted” A high true (active high) signal is high or a low true (active low) signal is low. “deasserted” A high true (active high) signal is low or a low true (active low) signal is high.
Introduction Part 2 Signal/Connection Descriptions 2.1 Introduction The input and output signals of the 56F8346 and 56F8146 are organized into functional groups, as detailed in Table 2-1 and as illustrated in Figure 2-1. In Table 2-2, each table row describes the signal or signals present on a pin.
Power VDD_IO Power VDDA_ADC Power VDDA_OSC_PLL Ground VSS Ground VSSA_ADC OCR_DIS Other Supply Ports VCAP1 - VCAP4 VPP1 & VPP2 1 PHASEA0 (TA0, GPIOC4) 1 1 PHASEB0 (TA1, GPIOC5) 1 5 1 INDEX0 (TA2, GPIOC6) 1 HOME0 (TA3, GPIOC7) 7 1 56F8346 1 1 1 1 4 1 CLKMODE 1 1 EXTAL 1 1 1 1 XTAL CLKO A0 - A5 (GPIOA8 - 13) External Address Bus or GPIO External Data Bus or GPIO A6 - A7 (GPIOE2 - 3) A8 - A15 (GPIOA0 - 7) GPIOB0 (A16) External Bus Control or GPIO 6 8 1 D7 - D15 (GPIOF
Introduction VDD_IO Power Power VDDA_ADC Power VDDA_OSC_PLL Ground VSS Ground VSSA_ADC OCR_DIS VCAP1 - VCAP4 Other Supply Ports External Data Bus or GPIO 1 5 1 PHASEB0 (TA1, GPIOC5) 1 INDEX0 (TA2, GPIOC6) 1 HOME0 (TA3, GPIOC7) 1 SCLK0 56F8146 1 1 1 1 (SCLK1, GPIOC0) EXTAL XTAL CLKO 1 1 1 1 9 WR PS (CS0)(GPIOD8) DS (CS1)(GPIOD9) GPIOD0 - 1 (CS2 - 3) 1 1 1 GPIO 6 3 4 PWMB0 - 5 ISB0 - 2 (GPIOD10 - 12) FAULTB0 - 3 PWMB or GPIO 8 ANA0 - 7 ADCA 5 1 TDI TDO TRST VREF ANB
2.2 Signal Pins After reset, each pin is configured for its primary function (listed first). Any alternate functionality must be programmed. Note: Signals in italics are NOT available in the 56F8146 device. If the “State During Reset” lists more than one state for a pin, the first state is the actual reset state. Other states show the reset condition of the alternate function, which you get if the alternate pin function is selected without changing the configuration of the alternate peripheral.
Signal Pins Table 2-2 Signal and Package Information for the 144 Pin LQFP Signal Name Pin No. Type State During Reset OCR_DIS 79 Input Input Signal Description On-Chip Regulator Disable — Tie this pin to VSS to enable the on-chip regulator Tie this pin to VDD to disable the on-chip regulator This pin is intended to be a static DC signal from power-up to shut down. Do not try to toggle this pin for power savings during operation.
Table 2-2 Signal and Package Information for the 144 Pin LQFP Signal Name Pin No. Type CLKO 3 Output State During Reset In reset, output is disabled Signal Description Clock Output — This pin outputs a buffered clock signal. Using the SIM CLKO Select Register (SIM_CLKOSR), this pin can be programmed as any of the following: disabled, CLK_MSTR (system clock), IPBus clock, oscillator output, prescaler clock and postscaler clock. Other signals are also available for test purposes. See Part 6.5.
Signal Pins Table 2-2 Signal and Package Information for the 144 Pin LQFP Signal Name Pin No. Type A6 17 Output State During Reset In reset, output is disabled, pull-up is enabled Signal Description Address Bus — A6 - A7 specify two of the address lines for external program or data memory accesses. Depending upon the state of the DRV bit in the EMI bus control register (BCR), A6 - A7 and EMI control signals are tri-stated when the external bus is inactive.
Table 2-2 Signal and Package Information for the 144 Pin LQFP Signal Name Pin No. Type State During Reset GPIOB0 33 Schmitt Input/ Output Input, pull-up enabled (A16) Output Signal Description Port B GPIO — This GPIO pin can be programmed as an input or output pin. Address Bus — A16 specifies one of the address lines for external program or data memory accesses.
Signal Pins Table 2-2 Signal and Package Information for the 144 Pin LQFP Signal Name Pin No. Type D7 28 Input/ Output (GPIOF0) State During Reset In reset, output is disabled, pull-up is enabled Input/ Output D8 (GPIOF1) 29 D9 (GPIOF2) 30 D10 (GPIOF3) 32 D11 (GPIOF4) 133 D12 (GPIOF5) 134 D13 (GPIOF6) 135 D14 (GPIOF7) 136 D15 137 Signal Description Data Bus — D7 - D14 specify part of the data for external program or data memory accesses.
Table 2-2 Signal and Package Information for the 144 Pin LQFP Signal Name Pin No. Type RD 45 Output State During Reset In reset, output is disabled, pull-up is enabled Signal Description Read Enable — RD is asserted during external memory read cycles. When RD is asserted low, pins D0 - D15 become inputs and an external device is enabled onto the data bus. When RD is deasserted high, the external data is latched inside the device. When RD is asserted, it qualifies the A0 - A16, PS, DS, and CSn pins.
Signal Pins Table 2-2 Signal and Package Information for the 144 Pin LQFP Signal Name Pin No. Type DS 47 Output (CS1) State During Reset In reset, output is disabled, pull-up is enabled Signal Description Data Memory Select — This signal is actually CS1 in the EMI, which is programmed at reset for compatibility with the 56F80x DS signal. DS is asserted low for external data memory access.
Table 2-2 Signal and Package Information for the 144 Pin LQFP Signal Name Pin No. Type RXD0 5 Input (GPIOE1) Input/ Output State During Reset Input, pull-up enabled Signal Description Receive Data — SCI0 receive data input Port E GPIO — This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is SCI output. To deactivate the internal pull-up resistor, clear bit 1 in the GPIOE_PUR register.
Signal Pins Table 2-2 Signal and Package Information for the 144 Pin LQFP State During Reset Signal Name Pin No. Type Signal Description TDO 124 Output In reset, output is disabled, pull-up is enabled Test Data Output — This tri-stateable output pin provides a serial output data stream from the JTAG/EOnCE port. It is driven in the shift-IR and shift-DR controller states, and changes on the falling edge of TCK.
Table 2-2 Signal and Package Information for the 144 Pin LQFP Signal Name Pin No. Type PHASEB0 140 Schmitt Input State During Reset Input, pull-up enabled Signal Description Phase B — Quadrature Decoder 0, PHASEB input (TA1) Schmitt Input/ Output TA1 — Timer A, Channel (GPIOC5) Schmitt Input/ Output Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is PHASEB0.
Signal Pins Table 2-2 Signal and Package Information for the 144 Pin LQFP Signal Name Pin No. Type State During Reset Signal Description SCLK0 130 Schmitt Input/ Output Input, pull-up enabled SPI 0 Serial Clock — In the master mode, this pin serves as an output, clocking slaved listeners. In slave mode, this pin serves as the data clock input. (GPIOE4) Schmitt Input/ Output Port E GPIO — This GPIO pin can be individually programmed as an input or output pin.
Table 2-2 Signal and Package Information for the 144 Pin LQFP Signal Name Pin No. Type SS0 129 Input (GPIOE7) State During Reset Input, pull-up enabled Input/ Output Signal Description SPI 0 Slave Select — SS0 is used in slave mode to indicate to the SPI module that the current transfer is to be received. Port E GPIO — This GPIO pin can be individually programmed as input or output pin. After reset, the default state is SS0.
Signal Pins Table 2-2 Signal and Package Information for the 144 Pin LQFP Signal Name Pin No. Type PHASEB1 7 Schmitt Input State During Reset Input, pull-up enabled Signal Description Phase B1 — Quadrature Decoder 1, PHASEB input for decoder 1. (TB1) Schmitt Input/ Output TB1 — Timer B, Channel 1 (MOSI1) Schmitt Input/ Output SPI 1 Master Out/Slave In — This serial data pin is an output from a master device and an input to a slave device.
Table 2-2 Signal and Package Information for the 144 Pin LQFP Signal Name Pin No. Type INDEX1 8 Schmitt Input State During Reset Input, pull-up enabled Signal Description Index1 — Quadrature Decoder 1, INDEX input (TB2) Schmitt Input/ Output TB2 — Timer B, Channel 2 (MISO1) Schmitt Input/ Output SPI 1 Master In/Slave Out — This serial data pin is an input to a master device and an output from a slave device.
Signal Pins Table 2-2 Signal and Package Information for the 144 Pin LQFP State During Reset Signal Name Pin No. Type PWMA0 62 Output PWMA0 - 5 — These are six PWMA outputs. PWMA1 64 PWMA2 65 In reset, output is disabled, pull-up is enabled PWMA3 67 PWMA4 68 PWMA5 70 ISA0 113 Schmitt Input Input, pull-up enabled ISA0 - 2 — These three input current status pins are used for top/bottom pulse width correction in complementary channel operation for PWMA.
Table 2-2 Signal and Package Information for the 144 Pin LQFP Signal Name Pin No.
Signal Pins Table 2-2 Signal and Package Information for the 144 Pin LQFP State During Reset Signal Name Pin No.
Table 2-2 Signal and Package Information for the 144 Pin LQFP Signal Name Pin No. Type State During Reset TD0 116 Schmitt Input/ Output Input, pull-up enabled (GPIOE10) TD1 (GPIOE11) 117 Signal Description TD0 -1 — Timer D, Channels 0 and 1 Port E GPIO — These GPIO pins can be individually programmed as input or output pins. Schmitt Input/ Output At reset, these pins default to Timer functionality.
Signal Pins Table 2-2 Signal and Package Information for the 144 Pin LQFP Signal Name Pin No. Type EXTBOOT 112 Schmitt Input State During Reset Input, pull-up enabled Signal Description External Boot — This input is tied to VDD to force the device to boot from off-chip memory (assuming that the on-chip Flash memory is not in a secure state). Otherwise, it is tied to ground. For details, see Table 4-4.
Part 3 On-Chip Clock Synthesis (OCCS) 3.1 Introduction Refer to the OCCS chapter of the 56F8300 Peripheral User Manual for a full description of the OCCS. The material contained here identifies the specific features of the OCCS design. Figure 3-1 shows the specific OCCS block diagram to reference in the OCCS chapter in the 56F8300 Peripheral User Manual.
External Clock Operation The crystal and associated components should be mounted as near as possible to the EXTAL and XTAL pins to minimize output distortion and start-up stabilization time.
Resonator Frequency = 4 - 8MHz (optimized for 8MHz) 3 Terminal 2 Terminal EXTAL XTAL EXTAL Rz CL1 XTAL Rz Sample External Ceramic Resonator Parameters: Rz = 750 KΩ CLKMODE = 0 CL2 C1 C2 Figure 3-3 Connecting a Ceramic Resonator Note: The OCCS_COHL bit must be set to 0 when a ceramic resonator is used. The reset condition on the OCCS_COHL bit is 0. Please see the COHL bit in the Oscillator Control (OSCTL) register, discussed in the 56F8300 Peripheral User Manual. 3.2.
Introduction This section provides memory maps for: • • Program Address Space, including the Interrupt Vector Table Data Address Space, including the EOnCE Memory and Peripheral Memory Maps On-chip memory sizes for each device are summarized in Table 4-1. Flash memories’ restrictions are identified in the “Use Restrictions” column of Table 4-1. Note: Data Flash and Program RAM are NOT available on the 56F8146 device.
Table 4-1 Chip Memory Configurations On-Chip Memory 56F8346 56F8146 Use Restrictions Data RAM 8KB 8KB None Program Boot Flash 8KB 8KB Erase / Program via Flash Interface unit and word to CDBW 4.2 Program Map The operating mode control bits (MA and MB) in the Operating Mode Register (OMR) control the Program memory map. At reset, these bits are set as indicated in Table 4-2. Table 4-4 shows the memory map configurations that are possible at reset.
Interrupt Vector Table in the 56F8346/56F8146). The EMI_MODE pin also affects the reset vector address, as provided in Table 4-4. Additional pins must be configured as address or chip select signals to access addresses at P:$10 0000 and above. Note: Program RAM is NOT available on the 56F8146 device.
interrupt priorities. All level 3 interrupts will be serviced before level 2, and so on. For a selected priority level, the lowest vector number has the highest priority. The location of the vector table is determined by the Vector Base Address (VBA) register. Please see Part 5.6.12 for the reset value of the VBA. In some configurations, the reset address and COP reset address will correspond to vector 0 and 1 of the interrupt vector table.
Interrupt Vector Table Table 4-5 Interrupt Vector Table Contents1 (Continued) Vector Number Priority Level Vector Base Address + FM 22 0-2 P:$2C FM Access Error Interrupt FM 23 0-2 P:$2E FM Command Complete FM 24 0-2 P:$30 FM Command, data and address Buffers Empty Peripheral Interrupt Function Reserved FLEXCAN 26 0-2 P:$34 FLEXCAN Bus Off FLEXCAN 27 0-2 P:$36 FLEXCAN Error FLEXCAN 28 0-2 P:$38 FLEXCAN Wake Up FLEXCAN 29 0-2 P:$3A FLEXCAN Message Buffer Interrupt GPI
Table 4-5 Interrupt Vector Table Contents1 (Continued) Peripheral DEC0 Vector Number Priority Level Vector Base Address + 50 0-2 P:$64 Interrupt Function Quadrature Decoder #0 INDEX Pulse Reserved TMRD 52 0-2 P:$68 Timer D, Channel 0 TMRD 53 0-2 P:$6A Timer D, Channel 1 TMRD 54 0-2 P:$6C Timer D, Channel 2 TMRD 55 0-2 P:$6E Timer D, Channel 3 TMRC 56 0-2 P:$70 Timer C, Channel 0 TMRC 57 0-2 P:$72 Timer C, Channel 1 TMRC 58 0-2 P:$74 Timer C, Channel 2 TMRC 59 0-2
Data Map 1. Two words are allocated for each entry in the vector table. This does not allow the full address range to be referenced from the vector table, providing only 19 bits of address. 2. If the VBA is set to 0200 (or VBA = 0000 for Mode 1, EMI_MODE = 0), the first two locations of the vector table are the chip reset addresses; therefore, these locations are not interrupt vectors. 2. 4.4 Data Map Note: Data Flash is NOT available on the 56F8146 device.
Program Memory buses. They are controlled by one set of banked registers. Data Memory Flash resides on the Data Memory buses and is controlled separately by own set of banked registers. The top nine words of the Program Memory Flash are treated as special memory locations. The content of these words is used to control the operation of the Flash Controller. Because these words are part of the Flash Memory content, their state is maintained during power-down and reset.
EOnCE Memory Map 4.
4.7 Peripheral Memory Mapped Registers On-chip peripheral registers are part of the data memory map on the 56800E series. These locations may be accessed with the same addressing modes used for ordinary Data memory, except all peripheral registers should be read/written using word accesses only. Table 4-9 summarizes base addresses for the set of peripherals on the 56F8346 and 56F8146 devices. Peripherals are listed in order of the base address.
Peripheral Memory Mapped Registers Table 4-9 Data Memory Peripheral Base Address Map Summary (Continued) Peripheral Prefix Base Address Table Number GPIO Port E GPIOE X:$00 F330 4-33 GPIO Port F GPIOF X:$00 F340 4-34 SIM SIM X:$00 F350 4-35 Power Supervisor LVI X:$00 F360 4-36 FM FM X:$00 F400 4-37 FlexCAN FC X:$00 F800 4-38 Table 4-10 External Memory Integration Registers Address Map (EMI_BASE = $00 F020) Register Acronym CSBAR 0 Address Offset $0 Register Description Chip Se
Table 4-10 External Memory Integration Registers Address Map (Continued) (EMI_BASE = $00 F020) Register Acronym Address Offset Register Description Reset Value CSOR 0 $8 Chip Select Option Register 0 0x5FCB programmed for chip select for program space, word wide, read and write, 11 waits CSOR 1 $9 Chip Select Option Register 1 0x5FAB programmed for chip select for data space, word wide, read and write, 11 waits CSOR 2 $A Chip Select Option Register 2 CSOR 3 $B Chip Select Option Register 3
Peripheral Memory Mapped Registers Table 4-11 Quad Timer A Registers Address Map (Continued) (TMRA_BASE = $00 F040) Register Acronym Address Offset Register Description TMRA0_CNTR $5 Counter Register TMRA0_CTRL $6 Control Register TMRA0_SCR $7 Status and Control Register TMRA0_CMPLD1 $8 Comparator Load Register 1 TMRA0_CMPLD2 $9 Comparator Load Register 2 TMRA0_COMSCR $A Comparator Status and Control Register Reserve TMRA1_CMP1 $10 Compare Register 1 TMRA1_CMP2 $11 Compare Registe
Table 4-11 Quad Timer A Registers Address Map (Continued) (TMRA_BASE = $00 F040) Register Acronym Address Offset Register Description TMRA3_CMP2 $31 Compare Register 2 TMRA3_CAP $32 Capture Register TMRA3_LOAD $33 Load Register TMRA3_HOLD $34 Hold Register TMRA3_CNTR $35 Counter Register TMRA3_CTRL $36 Control Register TMRA3_SCR $37 Status and Control Register TMRA3_CMPLD1 $38 Comparator Load Register 1 TMRA3_CMPLD2 $39 Comparator Load Register 2 TMRA3_COMSC $3A Comparator St
Peripheral Memory Mapped Registers Table 4-12 Quad Timer B Registers Address Map (Continued) (TMRB_BASE = $00 F080) Quad Timer B is NOT available in the 56F8146 device Register Acronym Address Offset Register Description TMRB1_CNTR $15 Counter Register TMRB1_CTRL $16 Control Register TMRB1_SCR $17 Status and Control Register TMRB1_CMPLD1 $18 Comparator Load Register 1 TMRB1_CMPLD2 $19 Comparator Load Register 2 TMRB1_COMSCR $1A Comparator Status and Control Register Reserved TMRB2_CMP1
Table 4-13 Quad Timer C Registers Address Map (TMRC_BASE = $00 F0C0) Register Acronym Address Offset Register Description TMRC0_CMP1 $0 Compare Register 1 TMRC0_CMP2 $1 Compare Register 2 TMRC0_CAP $2 Capture Register TMRC0_LOAD $3 Load Register TMRC0_HOLD $4 Hold Register TMRC0_CNTR $5 Counter Register TMRC0_CTRL $6 Control Register TMRC0_SCR $7 Status and Control Register TMRC0_CMPLD1 $8 Comparator Load Register 1 TMRC0_CMPLD2 $9 Comparator Load Register 2 TMRC0_COMSCR $A
Peripheral Memory Mapped Registers Table 4-13 Quad Timer C Registers Address Map (Continued) (TMRC_BASE = $00 F0C0) Register Acronym Address Offset Register Description TMRC2_SCR $27 Status and Control Register TMRC2_CMPLD1 $28 Comparator Load Register 1 TMRC2_CMPLD2 $29 Comparator Load Register 2 TMRC2_COMSCR $2A Comparator Status and Control Register Reserved TMRC3_CMP1 $30 Compare Register 1 TMRC3_CMP2 $31 Compare Register 2 TMRC3_CAP $32 Capture Register TMRC3_LOAD $33 Load Re
Table 4-14 Quad Timer D Registers Address Map (Continued) (TMRD_BASE = $00 F100) Quad Timer D is NOT available in the 56F8146 device Register Acronym Address Offset Register Description Reserved TMRD1_CMP1 $10 Compare Register 1 TMRD1_CMP2 $11 Compare Register 2 TMRD1_CAP $12 Capture Register TMRD1_LOAD $13 Load Register TMRD1_HOLD $14 Hold Register TMRD1_CNTR $15 Counter Register TMRD1_CTRL $16 Control Register TMRD1_SCR $17 Status and Control Register TMRD1_CMPLD1 $18 Comparat
Peripheral Memory Mapped Registers Table 4-14 Quad Timer D Registers Address Map (Continued) (TMRD_BASE = $00 F100) Quad Timer D is NOT available in the 56F8146 device Register Acronym Address Offset Register Description TMRD3_CTRL $36 Control Register TMRD3_SCR $37 Status and Control Register TMRD3_CMPLD1 $38 Comparator Load Register 1 TMRD3_CMPLD2 $39 Comparator Load Register 2 TMRD3_COMSCR $3A Comparator Status and Control Register Table 4-15 Pulse Width Modulator A Registers Address M
Table 4-16 Pulse Width Modulator B Registers Address Map (PWMB_BASE = $00 F160) Register Acronym Address Offset Register Description PWMB_PMCTL $0 Control Register PWMB_PMFCTL $1 Fault Control Register PWMB_PMFSA $2 Fault Status Acknowledge Register PWMB_PMOUT $3 Output Control Register PWMB_PMCNT $4 Counter Register PWMB_PWMCM $5 Counter Modulo Register PWMB_PWMVAL0 $6 Value Register 0 PWMB_PWMVAL1 $7 Value Register 1 PWMB_PWMVAL2 $8 Value Register 2 PWMB_PWMVAL3 $9 Value Re
Peripheral Memory Mapped Registers Table 4-17 Quadrature Decoder 0 Registers Address Map (Continued) (DEC0_BASE = $00 F180) Register Acronym Address Offset Register Description DEC0_REV $5 Revolution Counter Register DEC0_REVH $6 Revolution Hold Register DEC0_UPOS $7 Upper Position Counter Register DEC0_LPOS $8 Lower Position Counter Register DEC0_UPOSH $9 Upper Position Hold Register DEC0_LPOSH $A Lower Position Hold Register DEC0_UIR $B Upper Initialization Register DEC0_LIR $C
Table 4-19 Interrupt Control Registers Address Map (ITCN_BASE = $00 F1A0) Register Acronym Address Offset Register Description IPR 0 $0 Interrupt Priority Register 0 IPR 1 $1 Interrupt Priority Register 1 IPR 2 $2 Interrupt Priority Register 2 IPR 3 $3 Interrupt Priority Register 3 IPR 4 $4 Interrupt Priority Register 4 IPR 5 $5 Interrupt Priority Register 5 IPR 6 $6 Interrupt Priority Register 6 IPR 7 $7 Interrupt Priority Register 7 IPR 8 $8 Interrupt Priority Register 8 IPR
Peripheral Memory Mapped Registers Table 4-20 Analog-to-Digital Converter Registers Address Map (Continued) (ADCA_BASE = $00 F200) Register Acronym Address Offset Register Description ADCA_CR 2 $1 Control Register 2 ADCA_ZCC $2 Zero Crossing Control Register ADCA_LST 1 $3 Channel List Register 1 ADCA_LST 2 $4 Channel List Register 2 ADCA_SDIS $5 Sample Disable Register ADCA_STAT $6 Status Register ADCA_LSTAT $7 Limit Status Register ADCA_ZCSTAT $8 Zero Crossing Status Register AD
Table 4-20 Analog-to-Digital Converter Registers Address Map (Continued) (ADCA_BASE = $00 F200) Register Acronym Address Offset Register Description ADCA_OFS 1 $22 Offset Register 1 ADCA_OFS 2 $23 Offset Register 2 ADCA_OFS 3 $24 Offset Register 3 ADCA_OFS 4 $25 Offset Register 4 ADCA_OFS 5 $26 Offset Register 5 ADCA_OFS 6 $27 Offset Register 6 ADCA_OFS 7 $28 Offset Register 7 ADCA_POWER $29 Power Control Register ADCA_CAL $2A ADC Calibration Register Table 4-21 Analog-to-Digit
Peripheral Memory Mapped Registers Table 4-21 Analog-to-Digital Converter Registers Address Map (Continued) (ADCB_BASE = $00 F240) Register Acronym Address Offset Register Description ADCB_LLMT 3 $14 Low Limit Register 3 ADCB_LLMT 4 $15 Low Limit Register 4 ADCB_LLMT 5 $16 Low Limit Register 5 ADCB_LLMT 6 $17 Low Limit Register 6 ADCB_LLMT 7 $18 Low Limit Register 7 ADCB_HLMT 0 $19 High Limit Register 0 ADCB_HLMT 1 $1A High Limit Register 1 ADCB_HLMT 2 $1B High Limit Register 2 A
Table 4-23 Serial Communication Interface 0 Registers Address Map (SCI0_BASE = $00 F280) Register Acronym Address Offset Register Description SCI0_SCIBR $0 Baud Rate Register SCI0_SCICR $1 Control Register Reserved SCI0_SCISR $3 Status Register SCI0_SCIDR $4 Data Register Table 4-24 Serial Communication Interface 1 Registers Address Map (SCI1_BASE = $00 F290) Register Acronym Address Offset Register Description SCI1_SCIBR $0 Baud Rate Register SCI1_SCICR $1 Control Register Reserved
Peripheral Memory Mapped Registers Table 4-26 Serial Peripheral Interface 1 Registers Address Map (Continued) (SPI1_BASE = $00 F2B0) Register Acronym Address Offset SPI1_SPDTR $3 Register Description Data Transmitter Register Table 4-27 Computer Operating Properly Registers Address Map (COP_BASE = $00 F2C0) Register Acronym Address Offset Register Description COPCTL $0 Control Register COPTO $1 Time Out Register COPCTR $2 Counter Register Table 4-28 Clock Generation Module Registers Addres
Table 4-29 GPIOA Registers Address Map (Continued) (GPIOA_BASE = $00 F2E0) Register Acronym Address Offset Register Description Reset Value GPIOA_PPMODE $9 Push-Pull Mode Register 0 x 3FFF GPIOA_RAWDATA $A Raw Data Input Register — Table 4-30 GPIOB Registers Address Map (GPIOB_BASE = $00 F300) Register Acronym Address Offset Register Description Reset Value GPIOB_PUR $0 Pull-up Enable Register 0 x 00FF GPIOB_DR $1 Data Register 0 x 0000 GPIOB_DDR $2 Data Direction Register 0 x 000
Peripheral Memory Mapped Registers Table 4-31 GPIOC Registers Address Map (Continued) (GPIOC_BASE = $00 F310) Register Acronym Address Offset Register Description Reset Value GPIOC_IESR $8 Interrupt Edge-Sensitive Register 0 x 0000 GPIOC_PPMODE $9 Push-Pull Mode Register 0 x 07FF GPIOC_RAWDATA $A Raw Data Input Register — Table 4-32 GPIOD Registers Address Map (GPIOD_BASE = $00 F320) Register Acronym Address Offset Register Description Reset Value GPIOD_PUR $0 Pull-up Enable Register
Table 4-33 GPIOE Registers Address Map (Continued) (GPIOE_BASE = $00 F330) Register Acronym Address Offset Register Description Reset Value GPIOE_PPMODE $9 Push-Pull Mode Register 0 x 3FFF GPIOE_RAWDATA $A Raw Data Input Register — Table 4-34 GPIOF Registers Address Map (GPIOF_BASE = $00 F340) Register Acronym Address Offset Register Description Reset Value GPIOF_PUR $0 Pull-up Enable Register 0 x FFFF GPIOF_DR $1 Data Register 0 x 0000 GPIOF_DDR $2 Data Direction Register 0 x 000
Peripheral Memory Mapped Registers Table 4-35 System Integration Module Registers Address Map (Continued) (SIM_BASE = $00 F350) Register Acronym Address Offset Register Description SIM_CLKOSR $A Clock Out Select Register SIM_GPS $B Quad Decoder 1 / Timer B / SPI 1 Select Register SIM_PCE $C Peripheral Clock Enable Register SIM_ISALH $D I/O Short Address Location High Register SIM_ISALL $E I/O Short Address Location Low Register Table 4-36 Power Supervisor Registers Address Map (LVI_BASE =
Table 4-37 Flash Module Registers Address Map (Continued) (FM_BASE = $00 F400) Register Acronym Address Offset Register Description FMOPT 1 $1B 16-Bit Information Option Register 1 Not used FMOPT 2 $1C 16-Bit Information Option Register 2 Room temperature ADC reading of Temperature Sensor; value set during factory test Table 4-38 FlexCAN Registers Address Map (FC_BASE = $00 F800) FlexCAN is NOT available in the 56F8146 device Register Acronym FCMCR Address Offset $0 Register Description Module Co
Peripheral Memory Mapped Registers Table 4-38 FlexCAN Registers Address Map (Continued) (FC_BASE = $00 F800) FlexCAN is NOT available in the 56F8146 device Register Acronym Address Offset Register Description FCMB0_ID_LOW $42 Message Buffer 0 ID Low Register FCMB0_DATA $43 Message Buffer 0 Data Register FCMB0_DATA $44 Message Buffer 0 Data Register FCMB0_DATA $45 Message Buffer 0 Data Register FCMB0_DATA $46 Message Buffer 0 Data Register Reserved FCMSB1_CONTROL $48 Message Buffer 1 Con
Table 4-38 FlexCAN Registers Address Map (Continued) (FC_BASE = $00 F800) FlexCAN is NOT available in the 56F8146 device Register Acronym Address Offset Register Description FCMB4_ID_HIGH $61 Message Buffer 4 ID High Register FCMB4_ID_LOW $62 Message Buffer 4 ID Low Register FCMB4_DATA $63 Message Buffer 4 Data Register FCMB4_DATA $64 Message Buffer 4 Data Register FCMB4_DATA $65 Message Buffer 4 Data Register FCMB4_DATA $66 Message Buffer 4 Data Register Reserved FCMB5_CONTROL $68 Me
Peripheral Memory Mapped Registers Table 4-38 FlexCAN Registers Address Map (Continued) (FC_BASE = $00 F800) FlexCAN is NOT available in the 56F8146 device Register Acronym Address Offset Register Description FCMB8_CONTROL $80 Message Buffer 8 Control / Status Register FCMB8_ID_HIGH $81 Message Buffer 8 ID High Register FCMB8_ID_LOW $82 Message Buffer 8 ID Low Register FCMB8_DATA $83 Message Buffer 8 Data Register FCMB8_DATA $84 Message Buffer 8 Data Register FCMB8_DATA $85 Message Buff
Table 4-38 FlexCAN Registers Address Map (Continued) (FC_BASE = $00 F800) FlexCAN is NOT available in the 56F8146 device Register Acronym Address Offset Register Description FCMB11_DATA $9B Message Buffer 11 Data Register FCMB11_DATA $9C Message Buffer 11 Data Register FCMB11_DATA $9D Message Buffer 11 Data Register FCMB11_DATA $9E Message Buffer 11 Data Register Reserved FCMB12_CONTROL $A0 Message Buffer 12 Control / Status Register FCMB12_ID_HIGH $A1 Message Buffer 12 ID High Register
Factory Programmed Memory Table 4-38 FlexCAN Registers Address Map (Continued) (FC_BASE = $00 F800) FlexCAN is NOT available in the 56F8146 device Register Acronym Address Offset Register Description FCMB15_DATA $BB Message Buffer 15 Data Register FCMB15_DATA $BC Message Buffer 15 Data Register FCMB15_DATA $BD Message Buffer 15 Data Register FCMB15_DATA $BE Message Buffer 15 Data Register Reserved 4.
5.3 Functional Description The Interrupt Controller is a slave on the IPBus. It contains registers allowing each of the 82 interrupt sources to be set to one of four priority levels, excluding certain interrupts of fixed priority. Next, all of the interrupt requests of a given level are priority encoded to determine the lowest numerical value of the active interrupt requests for that level. Within a given priority level, zero is the highest priority, while number 81 is the lowest. 5.3.
Block Diagram 1. Setting the priority of the interrupt as level 2, with the appropriate field in the IPR registers 2. Setting the FIMn register to the appropriate vector number 3. Setting the FIVALn and FIVAHn registers with the address of the code for the fast interrupt When an interrupt occurs, its vector number is compared with the FIM0 and FIM1 register values. If a match occurs, and it is a level 2 interrupt, the ITCN handles it as a fast interrupt.
• Wait and Stop Modes During Wait and Stop modes, the system clocks and the 56800E core are turned off. The ITCN will signal a pending IRQ to the System Integration Module (SIM) to restart the clocks and service the IRQ. An IRQ can only wake up the core if the IRQ is enabled prior to entering the Wait or Stop mode. Also, the IRQA and IRQB signals automatically become low-level sensitive in these modes even if the control register bits are set to make them falling-edge sensitive.
Register Descriptions Table 5-3 ITCN Register Summary (ITCN_BASE = $00F1A0) (Continued) Register Acronym Base Address + Register Name Section Location IRQP2 $13 IRQ Pending Register 2 5.6.20 IRQP3 $14 IRQ Pending Register 3 5.6.21 IRQP4 $15 IRQ Pending Register 4 5.6.22 IRQP5 $16 IRQ Pending Register 5 5.6.23 Reserved $17 ICTL $1D Interrupt Control Register 5.6.30 Add.
Add. Register Offset Name $11 IRQP0 $12 IRQP1 $13 IRQP2 $14 IRQP3 $15 IRQP4 $16 IRQP5 15 14 13 12 11 10 9 R W R 8 6 5 4 3 2 1 0 1 PENDING [32:17] W R W R W R W R 7 PENDING [16:2] PENDING [48:33] PENDING [64:49] PENDING [80:65] 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 IRQB STATE IRQA STATE 1 PENDING [81] IRQB EDG IRQA EDG W Reserved $1D R ICTL INT IPIC VAB INT_DIS W = Reserved Figure 5-2 ITCN Register Map Summary 5.6.
Register Descriptions It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 1 10 = IRQ is priority level 2 11 = IRQ is priority level 3 5.6.1.4 Reserved—Bits 9–0 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 5.6.
• • 10 = IRQ is priority level 2 11 = IRQ is priority level 3 5.6.2.4 EOnCE Trace Buffer Interrupt Priority Level (TRBUF IPL)— Bits 1–0 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 1 through 3. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 1 10 = IRQ is priority level 2 11 = IRQ is priority level 3 5.6.
Register Descriptions • • • 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.3.3 Flash Memory Error Interrupt Priority Level (FMERR IPL)—Bits 11–10 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.3.
• • • 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.3.8 External IRQ A Interrupt Priority Level (IRQA IPL)—Bits 1–0 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.
Register Descriptions 5.6.4.3 GPIOF Interrupt Priority Level (GPIOF IPL)—Bits 11–10 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2two. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.4.4 FlexCAN Message Buffer Interrupt Priority Level (FCMSGBUF IPL)— Bits 9–8 This field is used to set the interrupt priority level for IRQs.
• • • 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.4.8 Reserved—Bits 1–0 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 5.6.
Register Descriptions 5.6.5.3 SPI1 Receiver Full Interrupt Priority Level (SPI1_RCV IPL)— Bits 11–10 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.5.4 Reserved—Bits 9–6 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 5.6.5.
5.6.6 Interrupt Priority Register 5 (IPR5) Base + $5 Read 15 14 13 DEC1_XIRQ IPL Write RESET 0 0 12 DEC1_HIRQ IPL 0 0 11 10 SCI1_RCV IPL 0 0 9 8 SCI1_RERR IPL 0 0 7 6 0 0 0 0 5 4 SCI1_TIDL IPL 0 0 3 2 SCI1_XMIT IPL 0 0 1 0 SPI0_XMIT IPL 0 0 Figure 5-8 Interrupt Priority Register 5 (IPR5) 5.6.6.1 Quadrature Decoder 1 INDEX Pulse Interrupt Priority Level (DEC1_XIRQ IPL)—Bits 15–14 This field is used to set the interrupt priority level for IRQs.
Register Descriptions 5.6.6.4 SCI 1 Receiver Error Interrupt Priority Level (SCI1_RERR IPL)— Bits 9–8 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.6.5 Reserved—Bits 7–6 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 5.6.6.
• • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.7 Interrupt Priority Register 6 (IPR6) Base + $6 15 14 13 12 11 10 9 8 7 6 Read TMRC0 IPL TMRD3 IPL TMRD2 IPL TMRD1 IPL 5 4 0 0 0 0 TMRD0 IPL Write RESET 0 0 0 0 0 0 0 0 0 0 3 2 DEC0_XIRQ IPL 0 0 1 0 DEC0_HIRQ IPL 0 0 Figure 5-9 Interrupt Priority Register 6 (IPR6) 5.6.7.
Register Descriptions • 11 = IRQ is priority level 2 5.6.7.4 Timer D, Channel 1 Interrupt Priority Level (TMRD1 IPL)—Bits 9–8 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.7.
5.6.8 Interrupt Priority Register 7 (IPR7) Base + $7 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read TMRA0 IPL TMRB3 IPL TMRB2 IPL TMRB1 IPL TMRB0 IPL TMRC3 IPL TMRC2 IPL TMRC1 IPL Write RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 5-10 Interrupt Priority Register (IPR7) 5.6.8.1 Timer A, Channel 0 Interrupt Priority Level (TMRA0 IPL)—Bits 15–14 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
Register Descriptions 5.6.8.5 Timer B, Channel 0 Interrupt Priority Level (TMRB0 IPL)—Bits 7–6 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.8.6 Timer C, Channel 3 Interrupt Priority Level (TMRC3 IPL)—Bits 5–4 This field is used to set the interrupt priority level for IRQs.
5.6.9 Interrupt Priority Register 8 (IPR8) Base + $8 Read 15 14 SCI0_RCV IPL Write RESET 0 0 13 12 SCI0_RERR IPL 0 0 11 10 0 0 0 0 9 8 SCI0_TIDL IPL 0 0 7 6 SCI0_XMIT IPL 0 0 5 4 TMRA3 IPL 0 0 3 2 TMRA2 IPL 0 0 1 0 TMRA1 IPL 0 0 Figure 5-11 Interrupt Priority Register 8 (IPR8) 5.6.9.1 SCI0 Receiver Full Interrupt Priority Level (SCI0_RCV IPL)—Bits 15–14 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
Register Descriptions 5.6.9.5 SCI0 Transmitter Empty Interrupt Priority Level (SCI0_XMIT IPL)— Bits 7–6 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.9.
5.6.10 Interrupt Priority Register 9 (IPR9) Base + $9 15 14 13 12 Read PWMA_F IPL PWMB_F IPL Write RESET 0 0 0 0 11 10 PWMA_RL IPL 0 0 9 8 PWM_RL IPL 0 0 7 6 5 4 ADCA_ZC IPL ABCB_ZC IPL 0 0 0 0 3 2 ADCA_CC IPL 0 0 1 0 ADCB_CC IPL 0 0 Figure 5-12 Interrupt Priority Register 9 (IPR9) 5.6.10.1 PWM A Fault Interrupt Priority Level (PWMA_F IPL)—Bits 15–14 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
Register Descriptions 5.6.10.5 ADC A Zero Crossing or Limit Error Interrupt Priority Level (ADCA_ZC IPL)—Bits 7–6 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.10.
5.6.11 Vector Base Address Register (VBA) Base + $A 15 14 13 Read 0 0 0 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 VECTOR BASE ADDRESS Write RESET 0 0 0 0 0 0 0 0 0 0 0 Figure 5-13 Vector Base Address Register (VBA) 5.6.11.1 Reserved—Bits 15–13 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 5.6.11.
Register Descriptions 5.6.13 Fast Interrupt 0 Vector Address Low Register (FIVAL0) Base + $C 15 14 13 12 11 10 Read 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 FAST INTERRUPT 0 VECTOR ADDRESS LOW Write RESET 0 0 0 0 0 0 0 0 0 0 Figure 5-15 Fast Interrupt 0 Vector Address Low Register (FIVAL0) 5.6.13.1 Fast Interrupt 0 Vector Address Low (FIVAL0)—Bits 15–0 The lower 16 bits of the vector address used for Fast Interrupt 0.
routine based on values in the Fast Interrupt Vector Address registers without having to go to a jump table first; see Part 5.3.3. IRQs used as fast interrupts must be set to priority level 2. Unexpected results will occur if a fast interrupt vector is set to any other priority. Fast interrupts automatically become the highest-priority level 2 interrupt, regardless of their location in the interrupt table, prior to being declared as fast interrupt. Fast Interrupt 0 has priority over Fast Interrupt 1.
Register Descriptions 5.6.18.1 IRQ Pending (PENDING)—Bits 16–2 This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2 through 81. • • 0 = IRQ pending for this vector number 1 = No IRQ pending for this vector number 5.6.18.2 Reserved—Bit 0 This bit is reserved or not implemented. It is read as 1 and cannot be modified by writing. 5.6.
5.6.21 IRQ Pending 3 Register (IRQP3) Base + $14 15 14 13 12 11 10 9 Read 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 PENDING [64:49] Write RESET 1 1 1 1 1 1 1 1 1 Figure 5-23 IRQ Pending 3 Register (IRQP3) 5.6.21.1 IRQ Pending (PENDING)—Bits 64–49 This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2 through 81. • • 0 = IRQ pending for this vector number 1 = No IRQ pending for this vector number 5.6.
Register Descriptions 5.6.23.1 Reserved—Bits 96–82 This bit field is reserved or not implemented. The bits are read as 1 and cannot be modified by writing. 5.6.23.2 IRQ Pending (PENDING)—Bit 81 This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2 through 81. • • 0 = IRQ pending for this vector number 1 = No IRQ pending for this vector number 5.6.24 Reserved—Base + 17 5.6.25 Reserved—Base + 18 5.6.26 Reserved—Base + 19 5.6.
• 1 = An interrupt is being sent to the 56800E core 5.6.30.2 Interrupt Priority Level (IPIC)—Bits 14–13 These read-only bits reflect the state of the new interrupt priority level bits being presented to the 56800E core at the time the last IRQ was taken. This field is only updated when the 56800E core jumps to a new interrupt service routine. Note: • • • • Nested interrupts may cause this field to be updated before the original interrupt service routine can read it.
Resets 5.6.30.9 IRQA Edge Pin (IRQA Edg)—Bit 0 This bit controls whether the external IRQA interrupt is edge- or level-sensitive. During Stop and Wait modes, it is automatically level-sensitive. • • 0 = IRQA interrupt is a low-level sensitive (default) 1 = IRQA interrupt is falling-edge sensitive. 5.7 Resets 5.7.1 Reset Handshake Timing The ITCN provides the 56800E core with a reset vector address whenever RESET is asserted.
• Enforcing Flash security These are discussed in more detail in the sections that follow. 6.
Operating Modes 6.3 Operating Modes Since the SIM is responsible for distributing clocks and resets across the chip, it must understand the various chip operating modes and take appropriate action. These are: • Reset Mode, which has two submodes: — POR and RESET operation The 56800E core and all peripherals are reset. This occurs when the internal POR is asserted or the RESET pin is asserted. — COP reset and software reset operation The 56800E core and all peripherals are reset.
6.5 Register Descriptions Table 6-1 SIM Registers (SIM_BASE = $00F350) Address Offset Address Acronym Register Name Section Location Base + $0 SIM_CONTROL Control Register 6.5.1 Base + $1 SIM_RSTSTS Reset Status Register 6.5.2 Base + $2 SIM_SCR0 Software Control Register 0 6.5.3 Base + $3 SIM_SCR1 Software Control Register 1 6.5.3 Base + $4 SIM_SCR2 Software Control Register 2 6.5.3 Base + $5 SIM_SCR3 Software Control Register 3 6.5.
Register Descriptions $C SIM_PCE $D SIM_ISALH $E SIM_ISALL R W R W R W EMI ADCB ADCA CAN DEC1 DEC0 1 1 1 1 1 1 TMRD TMRC TMRB TMRA 1 1 1 1 SCI1 SCI0 SPI1 SPI0 1 1 1 1 PWM B PWM A ISAL[23:22] ISAL[21:6] = Reserved Figure 6-2 SIM Register Map Summary (Continued) 6.5.
• 10 - The 56800E STOP instruction will not cause entry into Stop mode; STOP_DISABLE can then only be changed by resetting the device 11 - Same operation as 10 • 6.5.1.
Register Descriptions 6.5.2.5 Power-On Reset (POR)—Bit 2 When 1, the POR bit indicates a Power-On Reset occurred some time in the past. This bit can be cleared only by software or by another type of reset. Writing a 0 to this bit will set the bit, while writing a 1 to the bit position will clear the bit. In summary, if the bit is 1, the previous system reset was due to a Power-On Reset. 6.5.2.6 Reserved—Bits 1–0 This bit field is reserved or not implemented.
Base + $7 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 0 1 0 0 0 0 0 0 0 0 0 1 1 1 0 1 0 1 0 0 0 0 0 0 0 0 0 1 1 1 0 1 Write RESET Figure 6-7 Least Significant Half of JTAG ID (SIM_LSH_ID) 6.5.6 SIM Pull-up Disable Register (SIM_PUDR) Most of the pins on the chip have on-chip pull-up resistors. Pins which can operate as GPIO can have these resistors disabled via the GPIO function.
Register Descriptions 6.5.6.8 PWMB—Bit 8 This bit controls the pull-up resistors on the FAULTB0, FAULTB1, FAULTB2, and FAULTB3 pins. 6.5.6.9 PWMA0—Bit 7 This bit controls the pull-up resistors on the FAULTA0, FAULTA1, and FAULTA2 pins. 6.5.6.10 Reserved—Bit 6 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 6.5.6.11 CTRL—Bit 5 This bit controls the pull-up resistors on the WR and RD pins. 6.5.6.
6.5.7.2 • • 0 = Peripheral output function of GPIOB7 is defined to be A23 1 = Peripheral output function of GPIOB7 is defined to be the oscillator clock (MSTR_OSC, see Figure 3-4) 6.5.7.3 • • Alternate GPIOB Peripheral Function Select for A20 (A20)—Bit 6 0 = Peripheral output function of GPIOB4 is defined to be A20 1 = Peripheral output function of GPIOB4 is defined to be the prescaler clock (FREF, see Figure 3-4) 6.5.7.
Register Descriptions 6.5.8 GPIO Peripheral Select Register (SIM_GPS) The GPIO Peripheral Select register can be used to multiplex out any one of the three alternate peripherals for GPIOC. The default peripheral is Quad Decoder 1 and Quad Timer B (NOT available in the 56F8146 device); these peripherals work together. The four I/O pins associated with GPIOC can function as GPIO, Quad Decoder 1/Quad Timer B, or as SPI 1 signals.
Table 6-2 Control of Pads Using SIM_GPS Control 1 GPIOC_PER GPIOC_DTR SIM_GPS Quad Timer SCR Register OEN bits Control Registers GPIO Input 0 0 — — GPIO Output 0 1 — — Quad Timer Input / Quad Decoder Input 2 1 — 0 0 Quad Timer Output / Quad Decoder Input 3 1 — 0 1 SPI input 1 — 1 — SPI output 1 — 1 — Pin Function Comments See the “Switch Matrix for Inputs to the Timer” table in the 56F8300 Peripheral User Manual for the definition of the timer inputs based on the Quad D
Register Descriptions 6.5.8.3 GPIOC2 (C2)—Bit 2 This bit selects the alternate function for GPIOC2. • • 0 = INDEX1/TB2 (default) 1 = MISO1 6.5.8.4 GPIOC1 (C1)—Bit 1 This bit selects the alternate function for GPIOC1. • • 0 = PHASEB1/TB1 (default) 1 = MOSI1 6.5.8.5 GPIOC0 (C0)—Bit 0 This bit selects the alternate function for GPIOC0. • • 0 = PHASEA1/TB0 (default) 1 = SCLK1 6.5.
• 0 = The clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.4 FlexCAN Enable (CAN)—Bit 12 Each bit controls clocks to the indicated peripheral. • • 1 = Clocks are enabled 0 = The clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.5 Decoder 1 Enable (DEC1)—Bit 11 Each bit controls clocks to the indicated peripheral. • • 1 = Clocks are enabled 0 = The clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.
Register Descriptions 6.5.9.11 Serial Communications Interface 1 Enable (SCI1)—Bit 5 Each bit controls clocks to the indicated peripheral. • • 1 = Clocks are enabled 0 = The clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.12 Serial Communications Interface 0 Enable (SCI0)—Bit 4 Each bit controls clocks to the indicated peripheral. • • 1 = Clocks are enabled 0 = The clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.
Instruction Portion “Hard Coded” Address Portion 6 Bits from I/O Short Address Mode Instruction 16 Bits from SIM_ISALL Register 2 bits from SIM_ISALH Register Full 24-Bit for Short I/O Address Figure 6-13 I/O Short Address Determination With this register set, an interrupt driver can set the SIM_ISALL register pair to point to its peripheral registers and then use the I/O Short addressing mode to reference them.
Clock Generation Overview 6.5.10.2 Input/Output Short Address Low (ISAL[21:6])—Bit 15–0 This field represents the lower 16 address bits of the “hard coded” I/O short address. 6.6 Clock Generation Overview The SIM uses an internal master clock from the OCCS (CLKGEN) module to produce the peripheral and system (core and memory) clocks. The maximum master clock frequency is 120MHz. Peripheral and system clocks are generated at half the master clock frequency and therefore at a maximum 60MHz.
6.8 Stop and Wait Mode Disable Function Permanent Disable D Q D-FLOP C Reprogrammable Disable 56800E STOP_DIS D Q D-FLOP Clock Select C Reset R Note: Wait disable circuit is similar Figure 6-16 Internal Stop Disable Circuit The 56800E core contains both STOP and WAIT instructions. Both put the CPU to sleep. For lowest power consumption in Stop mode, the PLL can be shut down. This must be done explicitly before entering Stop mode, since there is no automatic mechanism for this.
Operation with Security Enabled Part 7 Security Features The 56F8346/56F8146 offer security features intended to prevent unauthorized users from reading the contents of the Flash Memory (FM) array. The Flash security consists of several hardware interlocks that block the means by which an unauthorized user could gain access to the Flash array. However, part of the security must lie with the user’s code.
mode. Therefore, the security feature cannot be used unless all executing code resides on-chip. When security is enabled, any attempt to override the default internal operating mode by asserting the EXTBOOT pin in conjunction with reset will be ignored. 7.2.2 Disabling EOnCE Access On-chip Flash can be read by issuing commands across the EOnCE port, which is the debug interface for the 56800E core.
Flash Access Blocking Mechanisms Flash Memory SYS_CLK input 2 clock DIVIDER 7 FMCLKD 7 7 FM_CLKDIV JTAG FM_ERASE Figure 7-1 JTAG to FM Connection for Lockout Recovery Two examples of FM_CLKDIV calculations follow. EXAMPLE 1: If the system clock is the 8MHz crystal frequency because the PLL has not been set up, the input clock will be below 12.8MHz, so PRDIV8 = FM_CLKDIV[6] = 0. Using the following equation yields a DIV value of 19 for a clock of 200kHz, and a DIV value of 20 for a clock of 190kHz.
Note: Once the lockout recovery sequence has completed, the user must reset both the JTAG TAP controller (by asserting TRST) and the device (by asserting external chip reset) to return to normal unsecured operation. 7.2.4 Product Analysis The recommended method of unsecuring a programmed device for product analysis of field failures is via the backdoor key access. The customer would need to supply Technical Support with the backdoor key and the protocol to access the backdoor routine in the Flash.
Configuration Table 8-1 56F8346 GPIO Ports Configuration GPIO Port Port Width Available Pins in 56F8346 A 14 14 14 pins - EMI Address pins EMI Address B 8 1 1 pin - EMI Address pin 7 pins - EMI Address pins - Not available in this package EMI Address N/A C 11 11 4 pins -DEC1 / TMRB / SPI1 4 pins -DEC0 / TMRA 3 pins -PWMA current sense DEC1 / TMRB DEC0 / TMRA PWMA current sense D 13 9 2 pins - EMI CSn 4 pins - EMI CSn - Not available in this package 2 pins - SCI1 2 pins - EMI CSn 3 pins
Table 8-2 56F8146 GPIO Ports Configuration GPIO Port Port Width Available Pins in 56F8146 E 14 11 2 pins - SCI0 2 pins - EMI Address pins 4 pins - SPI0 1 pin - TMRC 1 pin - TMRC - Not available in this package 2 pins - Dedicated GPIO 2 pins - TMRD - Not available in this package SCI0 EMI Address SPI0 TMRC N/A GPIO N/A F 16 16 16 pins - EMI Data EMI Data Peripheral Function Reset Function Table 8-3 GPIO External Signals Map Pins in shaded rows are not available in 56F8346/56F8146 Pins in itali
Configuration Table 8-3 GPIO External Signals Map (Continued) Pins in shaded rows are not available in 56F8346/56F8146 Pins in italics are NOT available in the 56F8146 device GPIO Port GPIO Bit Reset Function Functional Signal Package Pin 0 GPIO1 A16 33 1 N/A 2 N/A 3 N/A 4 N/A 5 N/A 6 N/A 7 N/A GPIOB 1This is a function of the EMI_MODE, EXTBOOT, and Flash security settings at reset.
Table 8-3 GPIO External Signals Map (Continued) Pins in shaded rows are not available in 56F8346/56F8146 Pins in italics are NOT available in the 56F8146 device GPIO Port GPIOD GPIO Bit Reset Function Functional Signal Package Pin 0 GPIO CS2 48 1 GPIO CS3 49 2 N/A 3 N/A 4 N/A 5 N/A 6 Peripheral TXD1 42 7 Peripheral RXD1 43 8 Peripheral PS / CS0 46 9 Peripheral DS / CS1 47 10 Peripheral ISB0 50 11 Peripheral ISB1 52 12 Peripheral ISB2 53 56F8346 Technical Dat
Configuration Table 8-3 GPIO External Signals Map (Continued) Pins in shaded rows are not available in 56F8346/56F8146 Pins in italics are NOT available in the 56F8146 device GPIO Port GPIO Bit Reset Function Functional Signal Package Pin 0 Peripheral TXD0 4 1 Peripheral RXD0 5 2 Peripheral A6 17 3 Peripheral A7 18 4 Peripheral SCLK0 130 5 Peripheral MOSI0 132 6 Peripheral MISO0 131 7 Peripheral SS0 129 8 Peripheral TC0 118 9 N/A 10 Peripheral TD0 116 11 Peri
Table 8-3 GPIO External Signals Map (Continued) Pins in shaded rows are not available in 56F8346/56F8146 Pins in italics are NOT available in the 56F8146 device GPIO Port GPIO Bit Reset Function Functional Signal Package Pin 0 Peripheral D7 28 1 Peripheral D8 29 2 Peripheral D9 30 3 Peripheral D10 32 4 Peripheral D11 133 5 Peripheral D12 134 6 Peripheral D13 135 7 Peripheral D14 136 8 Peripheral D15 137 9 Peripheral D0 59 10 Peripheral D1 60 11 Peripheral D
General Characteristics 5V-compatible I/O voltage levels (a standard 3.3V I/O is designed to receive a maximum voltage of 3.3V ± 10% during normal operation without causing damage). This 5V-tolerant capability therefore offers the power savings of 3.3V I/O levels combined with the ability to receive 5V levels without damage. Absolute maximum ratings in Table 10-1 are stress ratings only, and functional operation at the maximum is not guaranteed.
Table 10-1 Absolute Maximum Ratings (Continued) (VSS = VSSA_ADC = 0) Characteristic Symbol Ambient Temperature (Automotive) Notes Min Max Unit TA -40 125 °C Ambient Temperature (Industrial) TA -40 105 °C Junction Temperature (Automotive) TJ -40 150 °C Junction Temperature (Industrial) TJ -40 125 °C Storage Temperature (Automotive) TSTG -55 150 °C Storage Temperature (Industrial) TSTG -55 150 °C 1. If corresponding GPIO pin is configured as open drain.
General Characteristics Table 10-3 Thermal Characteristics6 Value Comments Characteristic Symbol Unit Notes 144-pin LQFP Junction to ambient (@1m/sec) RθJMA 43.8 °C/W 2 Junction to ambient Natural convection Four layer board (2s2p) RθJMA (2s2p) 40.8 °C/W 1,2 Junction to ambient (@1m/sec) Four layer board (2s2p) RθJMA 39.2 °C/W 1,2 Junction to case RθJC 11.
Table 10-4 Recommended Operating Conditions (VREFLO = 0V, VSS = VSSA_ADC = 0V, VDDA = VDDA_ADC = VDDA_OSC_PLL ) Characteristic Symbol Notes Min Typ Max Unit Internal Logic Core Supply Voltage VDD_CORE OCR_DIS is High 2.25 2.5 2.75 V Device Clock Frequency FSYSCLK 0 — 60 MHz Input High Voltage (digital) VIN Pin Groups 1, 2, 5, 6, 9, 10 2 — 5.5 V Input High Voltage (analog) VIHA Pin Group 13 2 — VDDA+0.3 V Input High Voltage (XTAL/EXTAL, VIHC Pin Group 11 VDDA-0.
DC Electrical Characteristics 10.2 DC Electrical Characteristics Note: The 56F8146 device is specified to meet Industrial requirements only; CAN is NOT available on the 56F8146 device. Table 10-5 DC Electrical Characteristics At Recommended Operating Conditions; see Table 10-4 Characteristic Symbol Notes Min Typ Max Unit Test Conditions Output High Voltage VOH 2.4 — — V IOH =IOHmax Output Low Voltage VOL — — 0.4 V IOL =IOLmax IIH Pin Groups 1, 2, 5, 6, 9 — 0 +/- 2.5 μA VIN = 3.
See Pin Groups in Table 10-1 Table 10-6 Power on Reset Low Voltage Parameters Characteristic Symbol Min Typ Max Units POR Trip Point POR 1.75 1.8 1.9 V LVI, 2.5 volt Supply, trip point1 VEI2.5 — 2.14 — V LVI, 3.3 volt supply, trip point2 VEI3.3 — 2.7 — V Bias Current I bias — 110 130 μA 1. When VDD_CORE drops below VEI2.5, an interrupt is generated. 2. When VDD_CORE drops below VEI3.3, an interrupt is generated.
DC Electrical Characteristics Table 10-8 Current Consumption per Power Supply Pin (Typical) On-Chip Regulator Disabled (OCR_DIS = High) Mode RUN1_MAC IDD_Core IDD_IO1 IDD_ADC IDD_OSC_PLL 150mA 13μA 50mA 2.5mA Test Conditions • 60MHz Device Clock • All peripheral clocks are enabled • All peripherals running • Continuous MAC instructions with fetches from Data RAM • ADC powered on and clocked Wait3 86mA 13μA 65μA 2.
Table 10-10. PLL Parameters Characteristics Symbol Min Typical Max Unit PLL Start-up time TPS 0.3 0.5 10 ms Resonator Start-up time TRS 0.1 0.18 1 ms Min-Max Period Variation TPV 120 — 200 ps Peak-to-Peak Jitter TPJ — — 175 ps Bias Current IBIAS — 1.5 2 mA IPD — 100 150 μA Quiescent Current, power-down mode 10.2.1 Temperature Sense Note: Temperature Sensor is NOT available in the 56F8146 device.
AC Electrical Characteristics 10.3 AC Electrical Characteristics Tests are conducted using the input levels specified in Table 10-5. Unless otherwise specified, propagation delays are measured from the 50% to the 50% point, and rise and fall times are measured between the 10% and 90% points, as shown in Figure 10-1. Low VIH Input Signal High 90% 50% 10% Midpoint1 VIL Fall Time Rise Time Note: The midpoint is VIL + (VIH – VIL)/2.
10.5 External Clock Operation Timing Table 10-13 External Clock Operation Timing Requirements1 Characteristic Symbol Min Typ Max Unit Frequency of operation (external clock driver)2 fosc 0 — 120 MHz Clock Pulse Width3 tPW 3.0 — — ns External clock input rise time4 trise — — 10 ns External clock input fall time5 tfall — — 10 ns 1. Parameters listed are guaranteed by design. 2. See Figure 10-3 for details on using the recommended connection of an external clock driver. 3.
Crystal Oscillator Timing 3. This is the minimum time required after the PLL set up is changed to ensure reliable operation. 10.7 Crystal Oscillator Timing Table 10-15 Crystal Oscillator Parameters Characteristic Symbol Min Typ Max Unit Crystal Start-up time TCS 4 5 10 ms Resonator Start-up time TRS 0.1 0.18 1 ms RESR — — 120 ohms Crystal Peak-to-Peak Jitter TD 70 — 250 ps Crystal Min-Max Period Variation TPV 0.12 — 1.
and DCAEO are used to make this duty cycle adjustment where needed. DCAOE and DCAEO are calculated as follows: DCAOE = 0.5 - MAX XTAL duty cycle, if ZSRC selects prescaler clock and the prescaler is set to ÷ 1 = 0.0 all other cases DCAEO = MIN XTAL duty cycle - 0.5, if ZSRC selects prescaler clock and the prescaler is set to ÷ 1 = 0.
External Memory Interface Timing Table 10-16 External Memory Interface Timing Characteristic Address Valid to WR Asserted WR Width Asserted to WR Deasserted Symbol Wait States Configuration D M WWS=0 -2.121 0.50 WWS>0 -1.805 0.75 + DCAOE WWS=0 -0.063 0.25 + DCAOE WWS>0 -0.253 0 WWS=0 -10.252 0.25 + DCAEO WWS=0 -2.868 0.00 WWS>0 -9.505 0.50 WWS>0 -2.552 0.25 + DCAOE -1.512 0.25 + DCAEO -2.047 0.25 + DCAOE -9.000 0.
3. Substitute BMDAR for MDAR if there is no chip select 4. MDAR is active in this calculation only when the chip select changes. 10.
Reset, Stop, Wait, Mode Select, and Interrupt Timing RESET tRA tRAZ A0–A15, D0–D15 tRDA First Fetch Figure 10-5 Asynchronous Reset Timing IRQA, IRQB tIRW Figure 10-6 External Interrupt Timing (Negative Edge-Sensitive) A0–A15 First Interrupt Instruction Execution tIDM IRQA, IRQB a) First Interrupt Instruction Execution General Purpose I/O Pin tIG IRQA, IRQB b) General Purpose I/O Figure 10-7 External Level-Sensitive Interrupt Timing 56F8346 Technical Data, Rev.
IRQA, IRQB tIRI A0–A15 First Interrupt Vector Instruction Fetch Figure 10-8 Interrupt from Wait State Timing tIW IRQA tIF A0–A15 First Instruction Fetch Not IRQA Interrupt Vector Figure 10-9 Recovery from Stop State Using Asynchronous Interrupt Timing 10.10 Serial Peripheral Interface (SPI) Timing Table 10-18 SPI Timing1 Characteristic Cycle time Master Slave Symbol Min Max Unit 50 50 — — ns ns — 25 — — ns ns — 100 — — ns ns 17.6 25 — — ns ns 24.
Serial Peripheral Interface (SPI) Timing Table 10-18 SPI Timing1 (Continued) Characteristic Symbol Data set-up time required for inputs Master Slave tDS Data hold time required for inputs Master Slave tDH Access time (time to data active from high-impedance state) Slave tA Disable time (hold time to high-impedance state) Slave tD Data Valid for outputs Master Slave (after enable edge) tDV Data invalid Master Slave tDI Rise time Master Slave tR Fall time Master Slave tF Min Max Unit 20
SS SS is held High on master (Input) tC tR tF tCL SCLK (CPOL = 0) (Output) tCH tF tR tCL SCLK (CPOL = 1) (Output) tDH tCH tDS MISO (Input) MSB in Bits 14–1 tDI MOSI (Output) Master MSB out tDV Bits 14 –1 tF LSB in tDI(ref) Master LSB out tR Figure 10-10 SPI Master Timing (CPHA = 0) 56F8346 Technical Data, Rev.
Serial Peripheral Interface (SPI) Timing SS (Input) SS is held High on master tC tF tR tCL SCLK (CPOL = 0) (Output) tCH tF tCL SCLK (CPOL = 1) (Output) tCH tDS tR MISO (Input) MSB in Bits 14 –1 tDI tDV (ref) MOSI (Output) tDH Master MSB out tDV Bits 14 – 1 tF LSB in tDI (ref) Master LSB out tR Figure 10-11 SPI Master Timing (CPHA = 1) 56F8346 Technical Data, Rev.
SS (Input) tC tF tCL SCLK (CPOL = 0) (Input) tELG tR tCH tELD tCL SCLK (CPOL = 1) (Input) tCH tA MISO (Output) Slave MSB out tF tR Bits 14 –1 tDS Slave LSB out tDV tDI tDH MOSI MSB in (Input) tD Bits 14 –1 tDI LSB in Figure 10-12 SPI Slave Timing (CPHA = 0) SS (Input) tF tC tR tCL SCLK (CPOL = 0) (Input) tCH tELG tELD tCL SCLK (CPOL = 1) (Input) tDV tCH tR tA MISO (Output) Slave MSB out Bits 14 –1 tDS tDV tDH MOSI (Input) tD tF MSB in Bits 14 –1 Slave LSB
Quad Timer Timing 10.11 Quad Timer Timing Table 10-19 Timer Timing1, 2 Characteristic Symbol Min Max Unit See Figure PIN 2T + 6 — ns 10-14 Timer input high / low period PINHL 1T + 3 — ns 10-14 Timer output period POUT 1T - 3 — ns 10-14 POUTHL 0.5T - 3 — ns 10-14 Timer input period Timer output high / low period 1. In the formulas listed, T = the clock cycle. For 60MHz operation, T = 16.67ns. 2. Parameters listed are guaranteed by design.
PPH PPH PPH PPH Phase A (Input) PHL PIN PHL Phase B PHL (Input) PIN PHL Figure 10-15 Quadrature Decoder Timing 10.13 Serial Communication Interface (SCI) Timing Table 10-21 SCI Timing1 Characteristic Symbol Min Max Unit See Figure BR — (fMAX/16) Mbps — RXD3 Pulse Width RXDPW 0.965/BR 1.04/BR ns 10-16 TXD4 Pulse Width TXDPW 0.965/BR 1.04/BR ns 10-17 Baud Rate2 1. Parameters listed are guaranteed by design. 2.
Controller Area Network (CAN) Timing TXD SCI receive data pin (Input) TXDPW Figure 10-17 TXD Pulse Width 10.14 Controller Area Network (CAN) Timing Note: CAN is NOT available in the 56F8146 device. Table 10-22 CAN Timing1 Characteristic Baud Rate Bus Wake Up detection Symbol Min Max Unit See Figure BRCAN — 1 Mbps — T WAKEUP 5 — μs 10-18 1. Parameters listed are guaranteed by design CAN_RX CAN receive data pin (Input) T WAKEUP Figure 10-18 Bus Wake Up Detection 10.
Table 10-23 JTAG Timing Characteristic Symbol Min Max Unit See Figure TMS, TDI data hold time tDH 5 — ns 10-20 TCK low to TDO data valid tDV — 30 ns 10-20 TCK low to TDO tri-state tTS — 30 ns 10-20 tTRST 2T2 — ns 10-21 TRST assertion time 1. TCK frequency of operation must be less than 1/8 the processor rate. 2.
Analog-to-Digital Converter (ADC) Parameters TRST (Input) tTRST Figure 10-21 TRST Timing Diagram 10.16 Analog-to-Digital Converter (ADC) Parameters Table 10-24 ADC Parameters Characteristic Symbol Min Typ Max Unit VADIN VREFL — VREFH V Resolution RES 12 — 12 Bits Integral Non-Linearity1 INL — +/- 2.4 +/- 3.2 LSB2 Differential Non-Linearity DNL — +/- 0.7 < +1 LSB2 Input voltages Monotonicity GUARANTEED ADC internal clock fADIC 0.
Table 10-24 ADC Parameters (Continued) Characteristic Symbol Min Typ Max Unit Calibration Factor 17 CF1 — -0.003141 — — Calibration Factor 27 CF2 — -17.6 — — — — -60 — dB Vcommon — (VREFH - VREFLO) / 2 — V SNR — 64.6 — db SINAD — 59.1 — db THD — 60.6 — db Spurious Free Dynamic Range SFDR — 61.1 — db Effective Number Of Bits8 ENOB — 9.
Equivalent Circuit for ADC Inputs Figure 10-22 ADC Absolute Error Over Processing and Temperature Extremes Before and After Calibration for VDCin = 0.60V and 2.70V Note: The absolute error data shown in the graphs above reflects the effects of both gain error and offset error.
at the same time that S3 is closed/open. When S1/S2 are closed & S3 is open, one input of the sample and hold circuit moves to VREFH - VREFH / 2, while the other charges to the analog input voltage. When the switches are flipped, the charge on C1 and C2 are averaged via S3, with the result that a single-ended analog input is switched to a differential voltage centered about VREFH - VREFH / 2. The switches switch on every cycle of the ADC clock (open one-half ADC clock, closed one-half ADC clock).
Power Consumption 10.18 Power Consumption This section provides additional detail which can be used to optimize power consumption for a given application.
• Cload is expressed in pF Because of the low duty cycle on most device pins, power dissipation due to capacitive loads was found to be fairly low when averaged over a period of time. The one possible exception to this is if the chip is using the external address and data buses at a rate approaching the maximum system rate. In this case, power from these buses can be significant. E, the external [static component], reflects the effects of placing resistive loads on the outputs of the device.
56F8346 Package and Pin-Out Information Part 11 Packaging 11.1 56F8346 Package and Pin-Out Information VSS EMI_MODE HOME0 INDEX0 PHASEB0 PHASEA0 A0 D15 D14 D13 D12 D11 MOSI0 MISO0 SCLK0 SS0 VCAP2 CAN_RX CAN_TX VPPI TDO TDI TMS TCK TRST VDD_IO TC0 TD1 TD0 ISA2 ISA1 ISA0 EXTBOOT ANB7 ANB6 ANB5 This section contains package and pin-out information for the 56F8346. This device comes in a 144-pin Low-profile Quad Flat Pack (LQFP).
Table 11-1 56F8346 144-Pin LQFP Package Identification by Pin Number Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name Pin No.
56F8146 Package and Pin-Out Information Table 11-1 56F8346 144-Pin LQFP Package Identification by Pin Number (Continued) Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name Pin No.
VSS EMI_MODE HOME0 INDEX0 PHASEB0 PHASEA0 A0 D15 D14 D13 D12 D11 MOSI0 MISO0 SCLK0 SS0 VCAP2 NC NC VPPI TDO TDI TMS TCK TRST VDD_IO TC0 GPIOE11 GPIOE10 GPIOC10 GPIOC9 GPIOC8 EXTBOOT ANB7 ANB6 ANB5 Orientation Mark ANB4 ANB3 ANB2 ANB1 ANB0 VSSA_ADC VDDA_ADC VREFH VREFP VREFMID VREFN VREFLO NC ANA7 ANA6 ANA5 ANA4 ANA3 ANA2 ANA1 ANA0 CLKMODE RESET RSTO VDD_IO VCAP3 EXTAL XTAL VDDA_OSC_PLL OCR_DIS D6 D5 D4 D3 NC NC 109 Pin 1 73 37 VSS VDD_IO PWMB3 PWMB4 PWMB5 TXD1 RXD1 WR RD PS DS GPIOD0 GPIOD1 ISB0 VCAP
56F8146 Package and Pin-Out Information Table 11-2 56F8146 144-Pin LQFP Package Identification by Pin Number (Continued) Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name Pin No.
Table 11-2 56F8146 144-Pin LQFP Package Identification by Pin Number (Continued) Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name Pin No.
56F8146 Package and Pin-Out Information 0.20 H B-C D 4X 144 PIN 1 INDEX 0.20 A B-C D 4X 36 TIPS 109 1 108 4X A A E1 C B 4 CL 5 E 7 140X E1/2 36 3 X X=B, C or D e VIEW A E/2 VIEW A e/2 73 37 72 D NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DATUMS B, C AND D TO BE DETERMINED AT DATUM H. 4. THE TOP PACKAGE BODY SIZE MAY BE SMALLER THAN THE BOTTOM PACKAGE SIZE BY A MAXIMUM OF 0.1 mm. 5.
Please see www.freescale.com for the most current case outline. Part 12 Design Considerations 12.
Electrical Design Considerations where: TT = Thermocouple temperature on top of package (oC) ΨJT = Thermal characterization parameter (oC)/W PD = Power dissipation in package (W) The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package.
• • Ensure that capacitor leads and associated printed circuit traces that connect to the chip VDD and VSS (GND) pins are less than 0.
Power Distribution and I/O Ring Implementation VDDA_OSC_PLL VDDA_ADC VDD REG VCAP REG I/O ADC CORE OSC VSS VREFH VREFP VREFMID VREFN VREFLO VSSA_ADC Figure 12-1 Power Management Part 13 Ordering Information Table 13-1 lists the pertinent information needed to place an order. Consult a Freescale Semiconductor sales office or authorized distributor to determine availability and to order parts.
How to Reach Us: Home Page: www.freescale.com E-mail: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.
