Datasheet

56F8346 Technical Data, Rev. 15
112 Freescale Semiconductor
Preliminary
6.5 Register Descriptions
Table 6-1 SIM Registers (SIM_BASE = $00F350)
Address Offset Address Acronym Register Name Section Location
Base + $0 SIM_CONTROL Control Register 6.5.1
Base + $1 SIM_RSTSTS Reset Status Register 6.5.2
Base + $2 SIM_SCR0 Software Control Register 0 6.5.3
Base + $3 SIM_SCR1 Software Control Register 1 6.5.3
Base + $4 SIM_SCR2 Software Control Register 2 6.5.3
Base + $5 SIM_SCR3 Software Control Register 3 6.5.3
Base + $6 SIM_MSH_ID Most Significant Half of JTAG ID 6.5.4
Base + $7 SIM_LSH_ID Least Significant Half of JTAG ID 6.5.5
Base + $8 SIM_PUDR Pull-up Disable Register 6.5.6
Reserved
Base + $A SIM_CLKOSR CLKO Select Register 6.5.7
Base + $B SIM_GPS GPIO Peripheral Select Register 6.5.7
Base + $C SIM_PCE Peripheral Clock Enable Register 6.5.8
Base + $D SIM_ISALH I/O Short Address Location High Register 6.5.9
Base + $E SIM_ISALL I/O Short Address Location Low Register 6.5.10
Add.
Offset
Register
Name
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
$0
SIM_
CONTROL
R
0 0 0 0 0 0 0 0 0
EMI_
MODE
ONCE
EBL
SW
RST
STOP_
DISABLE
WAIT_
DISABLE
W
$1
SIM_
RSTSTS
R
0 0 0 0 0 0 0 0 0 0
SWR COPR EXTR POR
0 0
W
$2 SIM_SCR0
R
FIELD
W
$3 SIM_SCR1
R
FIELD
W
$4 SIM_SCR2
R
FIELD
W
$5 SIM_SCR3
R
FIELD
W
$6
SIM_MSH_
ID
R
0 0 0 0 0 0 0 1 1 1 1 1 0 1 0 0
W
$7
SIM_LSH_ID
R
0 1 0 0 0 0 0 0 0 0 0 1 1 1 0 1
W
$8 SIM_PUDR
R
0
PWMA
1
CAN
EMI_
MODE
RESET
IRQ XBOOT PWMB
PWMA
0
0
CTRL
0
JTAG
0 0 0
W
Reserved
$A
SIM_
CLKOSR
R
0 0 0 0 0 0
A23
A22 A21 A20 CLKDIS CLKOSEL
W
$B SIM_GPS
R
0 0 0 0 0 0 0 0 0 0 0 0
C3 C2 C1 C0
W
Figure 6-2 SIM Register Map Summary