Datasheet

Register Descriptions
56F8346 Technical Data, Rev. 15
Freescale Semiconductor 113
Preliminary
6.5.1 SIM Control Register (SIM_CONTROL)
Figure 6-3 SIM Control Register (SIM_CONTROL)
6.5.1.1 Reserved—Bits 15–7
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.5.1.2 EMI_MODE (EMI_MODE)—Bit 6
This bit reflects the current (non-clocked) state of the EMI_MODE pin. During reset, this bit, coupled with
the EXTBOOT signal, is used to initialize address bits [19:16] either as GPIO or as address. These settings
can be explicitly overwritten using the appropriate GPIO peripheral enable register at any time after reset.
In addition, this pin can be used as a general purpose input pin after reset.
• 0 = External address bits [19:16] are initially programmed as GPIO
• 1 = When booted with EXTBOOT = 1, A[19:16] are initially programmed as address. If EXTBOOT is 0,
they are initialized as GPIO.
6.5.1.3 OnCE Enable (OnCE EBL)—Bit 5
• 0 = OnCE clock to 56800E core enabled when core TAP is enabled
• 1 = OnCE clock to 56800E core is always enabled
6.5.1.4 Software Reset (SWRST)—Bit 4
This bit is always read as 0. Writing a 1 to this field will cause the part to reset.
6.5.1.5 Stop Disable (STOP_DISABLE)—Bits 3–2
• 00 - STOP mode will be entered when the 56800E core executes a STOP instruction
• 01 - The 56800E STOP instruction will not cause entry into Stop mode; STOP_DISABLE can be
reprogrammed in the future
$C SIM_PCE
R
EMI ADCB ADCA CAN DEC1 DEC0 TMRD TMRC TMRB TMRA SCI1 SCI0 SPI1 SPI0
PWM
B
PWM
A
W
$D SIM_ISALH
R
1 1 1 1 1 1 1 1 1 1 1 1 1 1
ISAL[23:22]
W
$E SIM_ISALL
R
ISAL[21:6]
W
= Reserved
Base + $0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read
0 0 0 0 0 0 0 0 0
EMI_
MODE
ONCE
EBL
SW
RST
STOP_
DISABLE
WAIT_
DISABLE
Write
RESET
0000000000 000000
Figure 6-2 SIM Register Map Summary (Continued)