Datasheet

Register Descriptions
56F8346 Technical Data, Rev. 15
Freescale Semiconductor 115
Preliminary
6.5.2.5 Power-On Reset (POR)—Bit 2
When 1, the POR bit indicates a Power-On Reset occurred some time in the past. This bit can be cleared
only by software or by another type of reset. Writing a 0 to this bit will set the bit, while writing a 1 to the
bit position will clear the bit. In summary, if the bit is 1, the previous system reset was due to a Power-On
Reset.
6.5.2.6 Reserved—Bits 1–0
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.5.3 SIM Software Control Registers (SIM_SCR0, SIM_SCR1, SIM_SCR2,
and SIM_SCR3)
Only SIM_SCR0 is shown below. SIM_SCR1, SIM_SCR2, and SIM_SCR3 are identical in functionality.
Figure 6-5 SIM Software Control Register 0 (SIM_SCR0)
6.5.3.1 Software Control Data 1 (FIELD)—Bits 15–0
This register is reset only by the Power-On Reset (POR). It has no part-specific functionality and is
intended for use by a software developer to contain data that will be unaffected by the other reset sources
(RESET pin, software reset, and COP reset).
6.5.4 Most Significant Half of JTAG ID (SIM_MSH_ID)
This read-only register displays the most significant half of the JTAG ID for the chip. This register reads
$11F4.
Figure 6-6 Most Significant Half of JTAG ID (SIM_MSH_ID)
6.5.5 Least Significant Half of JTAG ID (SIM_LSH_ID)
This read-only register displays the least significant half of the JTAG ID for the chip. This register reads
$401D.
Base + $2
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read
FIELD
Write
POR
0 0 0 0 0 0 00000 0 0000
Base + $6
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read
0 0 0 0 0 0 0 1 1 1 1 1 0 1 0 0
Write
RESET
0 0 0 0 0 0 01111 1 0100