Datasheet

56F8346 Technical Data, Rev. 15

Freescale Semiconductor 119

Preliminary

6.5.8 GPIO Peripheral Select Register (SIM_GPS)

The GPIO Peripheral Select register can be used to multiplex out any one of the three alternate peripherals

for GPIOC. The default peripheral is Quad Decoder 1 and Quad Timer B (NOT available in the 56F8146

device); these peripherals work together.

The four I/O pins associated with GPIOC can function as GPIO, Quad Decoder 1/Quad Timer B, or as

SPI 1 signals. GPIO is not the default and is enabled/disabled via the GPIOC_PER, as shown in

Figure 6-10 and Table 6-2. When GPIOC[3:0] are programmed to operate as peripheral I/O, then the

choice between decoder/timer and SPI inputs/outputs is made in the SIM_GPS register and in conjunction

with the Quad Timer Status and Control Registers (SCR). The default state is for the peripheral function

of GPIOC[3:0] to be programmed as decoder functions. This can be changed by altering the appropriate

controls in the indicated registers.

Figure 6-10 Overall Control of Pads Using SIM_GPS Control

GPIOC_PER Register

GPIO Controlled

I/O

Pad Control

SIM_ GPS Register

Quad Timer Controlled

SPI Controlled