Datasheet

Architecture Block Diagram
56F8346 Technical Data, Rev. 15
Freescale Semiconductor 13
Preliminary
Figure 1-1 System Bus Interfaces
Note: Flash memories are encapsulated within the Flash Interface Unit (FIU). Flash control is accomplished
by the I/O to the FIU over the peripheral bus, while reads and writes are completed between the core
and the Flash memories.
Note: The primary data RAM port is 32 bits wide. Other data ports are 16 bits.
56800E
Program
Flash
Program
RAM
Data
RAM
EMI
Data
Flash
IPBus
Bridge
Boot
Flash
Flash
Interface
Units
NOT available on the 56F8146 device.
JTAG / EOnCE
5
pdb_m[15:0]
pab[20:0]
cdbw[13:0]
cdbr_m[31:0]
xab1[23:0]
xab2[23:0]
xdb2_m[15:0]
CHIP
TAP
Controller
TAP
Linking
Module
External
JTAG
Port
6
17
16
To Flash
Control Logic
IPBus
Address
Data
Control