Datasheet

56F8346 Technical Data, Rev. 15
142 Freescale Semiconductor
Preliminary
See Pin Groups in Table 10-1
Table 10-6 Power on Reset Low Voltage Parameters
Characteristic Symbol Min Typ Max Units
POR Trip Point
POR 1.75 1.8 1.9 V
LVI, 2.5 volt Supply, trip point
1
1. When V
DD_CORE
drops below V
EI2.5
, an interrupt is generated.
V
EI2.5
—2.14— V
LVI, 3.3 volt supply, trip point
2
2. When V
DD_CORE
drops below V
EI3.3
, an interrupt is generated.
V
EI3.3
—2.7— V
Bias Current
I
bias
—110130μA
Table 10-7 Current Consumption per Power Supply Pin (Typical)
On-Chip Regulator Enabled (OCR_DIS = Low)
Mode
I
DD_IO
1
1. No Output Switching
2. Includes Processor Core current supplied by internal voltage regulator
I
DD_ADC
I
DD_OSC_PLL
Test Conditions
RUN1_MAC
155mA 50mA 2.5mA
• 60MHz Device Clock
• All peripheral clocks are enabled
• All peripherals running
• Continuous MAC instructions with fetches from
Data RAM
• ADC powered on and clocked
Wait3
91mA 65μA2.5mA
• 60MHz Device Clock
• All peripheral clocks are enabled
• ADC powered off
Stop1
5.8mA 0μA155μA
• 8MHz Device Clock
• All peripheral clocks are off
• ADC powered off
• PLL powered off
Stop2
5.1mA 0μA145μA
• External Clock is off
• All peripheral clocks are off
• ADC powered off
• PLL powered off
R
ES
=
(V
REFH
- V
REFLO
) X 1
2
12
m