Datasheet

Crystal Oscillator Timing
56F8346 Technical Data, Rev. 15
Freescale Semiconductor 147
Preliminary
10.7 Crystal Oscillator Timing
10.8 External Memory Interface Timing
The External Memory Interface is designed to access static memory and peripheral devices. Figure 10-4
shows sample timing and parameters that are detailed in Table 10-16.
The timing of each parameter consists of both a fixed delay portion and a clock related portion, as well as
user controlled wait states. The equation:
t = D + P * (M + W)
should be used to determine the actual time of each parameter. The terms in this equation are defined as:
When using the XTAL clock input directly as the chip clock without prescaling (ZSRC selects prescaler
clock and prescaler is set to ÷ 1), the EMI quadrature clock is generated using both edges of the EXTAL
clock input. In this situation only, parameter values must be adjusted for the duty cycle at XTAL. DCAOE
3. This is the minimum time required after the PLL set up is changed to ensure reliable operation.
Table 10-15 Crystal Oscillator Parameters
Characteristic Symbol Min Typ Max Unit
Crystal Start-up time T
CS
4510ms
Resonator Start-up time T
RS
0.1 0.18 1 ms
Crystal ESR R
ESR
——120ohms
Crystal Peak-to-Peak Jitter T
D
70 — 250 ps
Crystal Min-Max Period Variation T
PV
0.12 — 1.5 ns
Resonator Peak-to-Peak Jitter T
RJ
——300ps
Resonator Min-Max Period Variation T
RP
——300ps
Bias Current, high-drive mode I
BIASH
—250290μA
Bias Current, low-drive mode I
BIASL
—80110μA
Quiescent Current, power-down mode I
PD
—0 1μA
t = Parameter delay time
D = Fixed portion of the delay, due to on-chip path delays
P = Period of the system clock, which determines the execution rate of the part
(i.e., when the device is operating at 60MHz, P = 16.67 ns)
M = Fixed portion of a clock period inherent in the design; this number is adjusted to account
for possible derating of clock duty cycle
W = Sum of the applicable wait state controls. The “Wait State Controls” column of
Table 10-16 shows the applicable controls for each parameter and the EMI chapter of the
56F8300 Peripheral User Manual details what each wait state field controls.