Datasheet

External Memory Interface Timing
56F8346 Technical Data, Rev. 15
Freescale Semiconductor 149
Preliminary
Table 10-16 External Memory Interface Timing
Characteristic Symbol
Wait States
Configuration
DM
Wait States
Controls
Unit
Address Valid to WR Asserted
t
AWR
WWS=0 -2.121 0.50
WWSS
ns
WWS>0 -1.805 0.75 + DCAOE
WR
Width Asserted to WR Deasserted
t
WR
WWS=0 -0.063 0.25 + DCAOE
WWS
ns
WWS>0 -0.253 0
Data Out Valid to WR
Asserted
t
DWR
WWS=0 -10.252 0.25 + DCAEO
WWSS
ns
WWS=0 -2.868 0.00
WWS>0 -9.505 0.50
WWS>0 -2.552 0.25 + DCAOE
Valid Data Out Hold Time after WR
Deasserted
t
DOH
-1.512 0.25 + DCAEO WWSH
ns
Valid Data Out Set-Up Time to WR
Deasserted
t
DOS
-2.047 0.25 + DCAOE
WWS, WWSS
ns
-9.000 0.50
Valid Address after WR
Deasserted
t
WAC
-3.888 0.25 + DCAEO WWSH
ns
RD Deasserted to Address Invalid
t
RDA
-2.922 0.00 RWSH
ns
Address Valid to RD Deasserted
t
ARDD
-1.645 1.00 RWSS, RWS
ns
Valid Input Data Hold after RD Deasserted
t
DRD
0.00
N/A
1
1. N/A, since device captures data before it deasserts RD
—
ns
RD Assertion Width
t
RD
0.257 1.00 RWS
ns
Address Valid to Input Data Valid
t
AD
-14.414 1.00
RWSS, RWS
ns
-19.299 1.25 + DCAOE
Address Valid to RD
Asserted
t
ARDA
-2.002 0.00 RWSS ns
RD Asserted to Input Data Valid
t
RDD
-12.411 1.00
RWSS, RWS
ns
-17.297 1.25 + DCAOE
WR
Deasserted to RD Asserted
t
WRRD
-1.323 0.25 + DCAEO
WWSH, RWSS
ns
RD Deasserted to RD Asserted
t
RDRD
-0.357
2
2. If RWSS = RWSH = 0, and the chip select does not change, then RD does not deassert during back-to-back reads.
0.00
RWSS, RWSH
MDAR
3, 4
ns
WR
Deasserted to WR Asserted
t
WRWR
WWS=0 -1.442 0.75 + DCAEO
WWSS,
WWSH
ns
WWS>0 -0.695 1.00
RD
Deasserted to WR Asserted
t
RDWR
WWS=0 -0.476 0.50 RWSH,
WWSS,
MDAR
3
ns
WWS>0 -0.160 0.75 + DCAOE