Datasheet

56F8346 Technical Data, Rev. 15
150 Freescale Semiconductor
Preliminary
10.9 Reset, Stop, Wait, Mode Select, and Interrupt Timing
3. Substitute BMDAR for MDAR if there is no chip select
4. MDAR is active in this calculation only when the chip select changes.
Table 10-17 Reset, Stop, Wait, Mode Select, and Interrupt Timing
1,2
1. In the formulas, T = clock cycle. For an operating frequency of 60MHz, T = 16.67ns. At 8MHz (used during Reset and Stop
modes), T = 125ns.
2. Parameters listed are guaranteed by design.
Characteristic Symbol
Typical
Min
Typical
Max
Unit See Figure
RESET
Assertion to Address, Data and Control Signals
High Impedance
t
RAZ
—21ns10-5
Minimum RESET
Assertion Duration
t
RA
16T — ns 10-5
RESET
Deassertion to First External Address Output
3
3. During Power-On Reset, it is possible to use the device’s internal reset stretching circuitry to extend this period to 2
21
T.
t
RDA
63T 64T ns 10-5
Edge-sensitive Interrupt Request Width
t
IRW
1.5T — ns 10-6
IRQA
, IRQB Assertion to External Data Memory Access
Out Valid, caused by first instruction execution in the
interrupt service routine
t
IDM
18T — ns 10-7
t
IDM - FAST
14T —
IRQA
, IRQB Assertion to General Purpose Output Valid,
caused by first instruction execution in the interrupt
service routine
t
IG
18T — ns 10-7
t
IG - FAST
14T —
Delay from IRQA Assertion (exiting Wait) to External Data
Memory access
4
4. The minimum is specified for the duration of an edge-sensitive IRQA interrupt required to recover from the Stop state. This is
not the minimum required so that the IRQA
interrupt is accepted.
t
IRI
22T — ns 10-8
t
IRI - FAST
18T —
Delay from IRQA Assertion to External Data Memory
Access (exiting Stop)
t
IF
22T — ns 10-9
t
IF - FAST
18T —
IRQA
Width Assertion to Recover from Stop State
5
5. The interrupt instruction fetch is visible on the pins only in Mode 3.
t
IW
1.5T — ns 10-9