Datasheet

56F8346 Technical Data, Rev. 15
152 Freescale Semiconductor
Preliminary
Figure 10-8 Interrupt from Wait State Timing
Figure 10-9 Recovery from Stop State Using Asynchronous Interrupt Timing
10.10 Serial Peripheral Interface (SPI) Timing
Table 10-18 SPI Timing
1
Characteristic Symbol Min Max Unit See Figure
Cycle time
Master
Slave
t
C
50
50
—
—
ns
ns
10-10, 10-11,
10-12, 10-13
Enable lead time
Master
Slave
t
ELD
—
25
—
—
ns
ns
10-13
Enable lag time
Master
Slave
t
ELG
—
100
—
—
ns
ns
10-13
Clock (SCK) high time
Master
Slave
t
CH
17.6
25
—
—
ns
ns
10-10, 10-11,
10-12, 10-13
Clock (SCK) low time
Master
Slave
t
CL
24.1
25
—
—
ns
ns
10-13
Instruction Fetch
t
IRI
IRQA,
IRQB
First Interrupt Vector
A0–A15
Not IRQA Interrupt Vector
t
IW
IRQA
t
IF
A0–A15
First Instruction Fetch