Datasheet

Controller Area Network (CAN) Timing
56F8346 Technical Data, Rev. 15
Freescale Semiconductor 159
Preliminary
Figure 10-17 TXD Pulse Width
10.14 Controller Area Network (CAN) Timing
Note: CAN is NOT available in the 56F8146 device.
Figure 10-18 Bus Wake Up Detection
10.15 JTAG Timing
Table 10-22 CAN Timing
1
1. Parameters listed are guaranteed by design
Characteristic Symbol Min Max Unit See Figure
Baud Rate
BR
CAN
—
1 Mbps
—
Bus Wake Up detection
T
WAKEUP
5
—
μs 10-18
Table 10-23 JTAG Timing
Characteristic Symbol Min Max Unit See Figure
TCK frequency of operation
using EOnCE
1
f
OP
DC SYS_CLK/8 MHz 10-19
TCK frequency of operation not
using EOnCE
1
f
OP
DC SYS_CLK/4 MHz 10-19
TCK clock pulse width
t
PW
50 — ns 10-19
TMS, TDI data set-up time
t
DS
5—ns10-20
TXD
PW
TXD
SCI receive
data pin
(Input)
T
WAKEUP
CAN_RX
CAN receive
data pin
(Input)