Datasheet

56F8346 Technical Data, Rev. 15
46 Freescale Semiconductor
Preliminary
interrupt priorities. All level 3 interrupts will be serviced before level 2, and so on. For a selected priority
level, the lowest vector number has the highest priority.
The location of the vector table is determined by the Vector Base Address (VBA) register. Please see Part
5.6.12 for the reset value of the VBA.
In some configurations, the reset address and COP reset address will correspond to vector 0 and 1 of the
interrupt vector table. In these instances, the first two locations in the vector table must contain branch or
JMP instructions. All other entries must contain JSR instructions.
Note: PWMA, FlexCAN, Quadrature Decoder 1, and Quad Timers B and D are NOT available on the
56F8146 device.
Table 4-5 Interrupt Vector Table Contents
1
Peripheral
Vector
Number
Priority
Level
Vector Base
Address +
Interrupt Function
Reserved for Reset Overlay
2
Reserved for COP Reset Overlay
2
core 2 3 P:$04 Illegal Instruction
core 3 3 P:$06 SW Interrupt 3
core 4 3 P:$08 HW Stack Overflow
core 5 3 P:$0A Misaligned Long Word Access
core 6 1-3 P:$0C OnCE Step Counter
core 7 1-3 P:$0E OnCE Breakpoint Unit 0
Reserved
core 9 1-3 P:$12 OnCE Trace Buffer
core 10 1-3 P:$14 OnCE Transmit Register Empty
core 11 1-3 P:$16 OnCE Receive Register Full
Reserved
core 14 2 P:$1C SW Interrupt 2
core 15 1 P:$1E SW Interrupt 1
core 16 0 P:$20 SW Interrupt 0
core 17 0-2 P:$22 IRQA
core 18 0-2 P:$24 IRQB
Reserved
LVI 20 0-2 P:$28 Low Voltage Detector (power sense)
PLL 21 0-2 P:$2A PLL