Datasheet

Peripheral Memory Mapped Registers
56F8346 Technical Data, Rev. 15
Freescale Semiconductor 53
Preliminary
GPIO Port E GPIOE X:$00 F330 4-33
GPIO Port F GPIOF X:$00 F340 4-34
SIM SIM X:$00 F350 4-35
Power Supervisor LVI X:$00 F360 4-36
FM FM X:$00 F400 4-37
FlexCAN FC X:$00 F800 4-38
Table 4-10 External Memory Integration Registers Address Map
(EMI_BASE = $00 F020)
Register Acronym Address Offset Register Description Reset Value
CSBAR 0 $0 Chip Select Base Address Register 0 0x0004 = 64K when
EXT_BOOT = 0 or
EMI_MODE = 0
0x0008 = 1M when
EMI_MODE = 1
(Selects entire program
space for CS0)
Note that A17-A19 are not
available in the package
CSBAR 1 $1 Chip Select Base Address Register 1 0x0004 = 64K when
EMI_MODE = 0
0x0008 = 1M when
EMI_MODE = 1
(Selects A0-A19
addressable data space for
CS1)
Note that A17-A19 are not
available in the package
CSBAR 2 $2 Chip Select Base Address Register 2
CSBAR 3 $3 Chip Select Base Address Register 3
CSBAR 4 $4 Chip Select Base Address Register 4
CSBAR 5 $5 Chip Select Base Address Register 5
CSBAR 6 $6 Chip Select Base Address Register 6
CSBAR 7 $7 Chip Select Base Address Register 7
Table 4-9 Data Memory Peripheral Base Address Map Summary (Continued)
Peripheral Prefix Base Address Table Number