Datasheet

Peripheral Memory Mapped Registers

56F8346 Technical Data, Rev. 15

Freescale Semiconductor 55

Preliminary

TMRA0_CNTR $5 Counter Register

TMRA0_CTRL $6 Control Register

TMRA0_SCR $7 Status and Control Register

TMRA0_CMPLD1 $8 Comparator Load Register 1

TMRA0_CMPLD2 $9 Comparator Load Register 2

TMRA0_COMSCR $A Comparator Status and Control Register

Reserve

TMRA1_CMP1 $10 Compare Register 1

TMRA1_CMP2 $11 Compare Register 2

TMRA1_CAP $12 Capture Register

TMRA1_LOAD $13 Load Register

TMRA1_HOLD $14 Hold Register

TMRA1_CNTR $15 Counter Register

TMRA1_CTRL $16 Control Register

TMRA1_SCR $17 Status and Control Register

TMRA1_CMPLD1 $18 Comparator Load Register 1

TMRA1_CMPLD2 $19 Comparator Load Register 2

TMRA1_COMSCR $1A Comparator Status and Control Register

Reserved

TMRA2_CMP1 $20 Compare Register 1

TMRA2_CMP2 $21 Compare Register 2

TMRA2_CAP $22 Capture Register

TMRA2_LOAD $23 Load Register

TMRA2_HOLD $24 Hold Register

TMRA2_CNTR $25 Counter Register

TMRA2_CTRL $26 Control Register

TMRA2_SCR $27 Status and Control Register

TMRA2_CMPLD1 $28 Comparator Load Register 1

TMRA2_CMPLD2 $29 Comparator Load Register 2

TMRA2_COMSCR $2A Comparator Status and Control Register

Reserved

TMRA3_CMP1 $30 Compare Register 1

Table 4-11 Quad Timer A Registers Address Map (Continued)

(TMRA_BASE = $00 F040)