Datasheet

Peripheral Memory Mapped Registers

56F8346 Technical Data, Rev. 15

Freescale Semiconductor 57

Preliminary

TMRB1_CNTR $15 Counter Register

TMRB1_CTRL $16 Control Register

TMRB1_SCR $17 Status and Control Register

TMRB1_CMPLD1 $18 Comparator Load Register 1

TMRB1_CMPLD2 $19 Comparator Load Register 2

TMRB1_COMSCR $1A Comparator Status and Control Register

Reserved

TMRB2_CMP1 $20 Compare Register 1

TMRB2_CMP2 $21 Compare Register 2

TMRB2_CAP $22 Capture Register

TMRB2_LOAD $23 Load Register

TMRB2_HOLD $24 Hold Register

TMRB2_CNTR $25 Counter Register

TMRB2_CTRL $26 Control Register

TMRB2_SCR $27 Status and Control Register

TMRB2_CMPLD1 $28 Comparator Load Register 1

TMRB2_CMPLD2 $29 Comparator Load Register 2

TMRB2_COMSCR $2A Comparator Status and Control Register

Reserved

TMRB3_CMP1 $30 Compare Register 1

TMRB3_CMP2 $31 Compare Register 2

TMRB3_CAP $32 Capture Register

TMRB3_LOAD $33 Load Register

TMRB3_HOLD $34 Hold Register

TMRB3_CNTR $35 Counter Register

TMRB3_CTRL $36 Control Register

TMRB3_SCR $37 Status and Control Register

TMRB3_CMPLD1 $38 Comparator Load Register 1

TMRB3_CMPLD2 $39 Comparator Load Register 2

TMRB3_COMSCR $3A Comparator Status and Control Register

Table 4-12 Quad Timer B Registers Address Map (Continued)

(TMRB_BASE = $00 F080)

Quad Timer B is NOT available in the 56F8146 device