Datasheet

Peripheral Memory Mapped Registers

56F8346 Technical Data, Rev. 15

Freescale Semiconductor 59

Preliminary

TMRC2_SCR $27 Status and Control Register

TMRC2_CMPLD1 $28 Comparator Load Register 1

TMRC2_CMPLD2 $29 Comparator Load Register 2

TMRC2_COMSCR $2A Comparator Status and Control Register

Reserved

TMRC3_CMP1 $30 Compare Register 1

TMRC3_CMP2 $31 Compare Register 2

TMRC3_CAP $32 Capture Register

TMRC3_LOAD $33 Load Register

TMRC3_HOLD $34 Hold Register

TMRC3_CNTR $35 Counter Register

TMRC3_CTRL $36 Control Register

TMRC3_SCR $37 Status and Control Register

TMRC3_CMPLD1 $38 Comparator Load Register 1

TMRC3_CMPLD2 $39 Comparator Load Register 2

TMRC3_COMSCR $3A Comparator Status and Control Register

Table 4-14 Quad Timer D Registers Address Map

(TMRD_BASE = $00 F100)

Quad Timer D is NOT available in the 56F8146 device

TMRD0_CMP1 $0 Compare Register 1

TMRD0_CMP2 $1 Compare Register 2

TMRD0_CAP $2 Capture Register

TMRD0_LOAD $3 Load Register

TMRD0_HOLD $4 Hold Register

TMRD0_CNTR $5 Counter Register

TMRD0_CTRL $6 Control Register

TMRD0_SCR $7 Status and Control Register

TMRD0_CMPLD1 $8 Comparator Load Register 1

TMRD0_CMPLD2 $9 Comparator Load Register 2

TMRD0_COMSCR $A Comparator Status and Control Register

Table 4-13 Quad Timer C Registers Address Map (Continued)

(TMRC_BASE = $00 F0C0)