Datasheet

56F8346 Technical Data, Rev. 15
60 Freescale Semiconductor
Preliminary
Reserved
TMRD1_CMP1 $10 Compare Register 1
TMRD1_CMP2 $11 Compare Register 2
TMRD1_CAP $12 Capture Register
TMRD1_LOAD $13 Load Register
TMRD1_HOLD $14 Hold Register
TMRD1_CNTR $15 Counter Register
TMRD1_CTRL $16 Control Register
TMRD1_SCR $17 Status and Control Register
TMRD1_CMPLD1 $18 Comparator Load Register 1
TMRD1_CMPLD2 $19 Comparator Load Register 2
TMRD1_COMSCR $1A Comparator Status and Control Register
Reserved
TMRD2_CMP1 $20 Compare Register 1
TMRD2_CMP2 $21 Compare Register 2
TMRD2_CAP $22 Capture Register
TMRD2_LOAD $23 Load Register
TMRD2_HOLD $24 Hold Register
TMRD2_CNTR $25 Counter Register
TMRD2_CTRL $26 Control Register
TMRD2_SCR $27 Status and Control Register
TMRD2_CMPLD1 $28 Comparator Load Register 1
TMRD2_CMPLD2 $29 Comparator Load Register 2
TMRD2_COMSCR $2A Comparator Status and Control Register
Reserved
TMRD3_CMP1 $30 Compare Register 1
TMRD3_CMP2 $31 Compare Register 2
TMRD3_CAP $32 Capture Register
TMRD3_LOAD $33 Load Register
TMRD3_HOLD $34 Hold Register
TMRD3_CNTR $35 Counter Register
Table 4-14 Quad Timer D Registers Address Map (Continued)
(TMRD_BASE = $00 F100)
Quad Timer D is NOT available in the 56F8146 device
Register Acronym Address Offset Register Description