Datasheet

Peripheral Memory Mapped Registers

56F8346 Technical Data, Rev. 15

Freescale Semiconductor 61

Preliminary

TMRD3_CTRL $36 Control Register

TMRD3_SCR $37 Status and Control Register

TMRD3_CMPLD1 $38 Comparator Load Register 1

TMRD3_CMPLD2 $39 Comparator Load Register 2

TMRD3_COMSCR $3A Comparator Status and Control Register

Table 4-15 Pulse Width Modulator A Registers Address Map

(PWMA_BASE = $00 F140)

PWMA is NOT available in the 56F8146 device

PWMA_PMCTL $0 Control Register

PWMA_PMFCTL $1 Fault Control Register

PWMA_PMFSA $2 Fault Status Acknowledge Register

PWMA_PMOUT $3 Output Control Register

PWMA_PMCNT $4 Counter Register

PWMA_PWMCM $5 Counter Modulo Register

PWMA_PWMVAL0 $6 Value Register 0

PWMA_PWMVAL1 $7 Value Register 1

PWMA_PWMVAL2 $8 Value Register 2

PWMA_PWMVAL3 $9 Value Register 3

PWMA_PWMVAL4 $A Value Register 4

PWMA_PWMVAL5 $B Value Register 5

PWMA_PMDEADTM $C Dead Time Register

PWMA_PMDISMAP1 $D Disable Mapping Register 1

PWMA_PMDISMAP2 $E Disable Mapping Register 2

PWMA_PMCFG $F Configure Register

PWMA_PMCCR $10 Channel Control Register

PWMA_PMPORT $11 Port Register

PWMA_PMICCR $12 PWM Internal Correction Control Register

Table 4-14 Quad Timer D Registers Address Map (Continued)

(TMRD_BASE = $00 F100)

Quad Timer D is NOT available in the 56F8146 device