Datasheet

Peripheral Memory Mapped Registers
56F8346 Technical Data, Rev. 15
Freescale Semiconductor 69
Preliminary
SPI1_SPDTR $3 Data Transmitter Register
Table 4-27 Computer Operating Properly Registers Address Map
(COP_BASE = $00 F2C0)
Register Acronym Address Offset Register Description
COPCTL $0 Control Register
COPTO $1 Time Out Register
COPCTR $2 Counter Register
Table 4-28 Clock Generation Module Registers Address Map
(CLKGEN_BASE = $00 F2D0)
Register Acronym Address Offset Register Description
PLLCR $0 Control Register
PLLDB $1 Divide-By Register
PLLSR $2 Status Register
Reserved
SHUTDOWN $4 Shutdown Register
OSCTL $5 Oscillator Control Register
Table 4-29 GPIOA Registers Address Map
(GPIOA_BASE = $00 F2E0)
Register Acronym
Address Offset Register Description Reset Value
GPIOA_PUR
$0 Pull-up Enable Register
0 x 3FFF
GPIOA_DR
$1 Data Register
0 x 0000
GPIOA_DDR
$2 Data Direction Register
0 x 0000
GPIOA_PER
$3 Peripheral Enable Register
0 x 3FFF
GPIOA_IAR
$4 Interrupt Assert Register
0 x 0000
GPIOA_IENR
$5 Interrupt Enable Register
0 x 0000
GPIOA_IPOLR
$6 Interrupt Polarity Register
0 x 0000
GPIOA_IPR
$7 Interrupt Pending Register
0 x 0000
GPIOA_IESR
$8 Interrupt Edge-Sensitive Register
0 x 0000
Table 4-26 Serial Peripheral Interface 1 Registers Address Map (Continued)
(SPI1_BASE = $00 F2B0)
Register Acronym Address Offset Register Description