Datasheet

56F8346 Technical Data, Rev. 15
84 Freescale Semiconductor
Preliminary
5.6.1 Interrupt Priority Register 0 (IPR0)
Figure 5-3 Interrupt Priority Register 0 (IPR0)
5.6.1.1 Reserved—Bits 15–14
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.1.2 EOnCE Breakpoint Unit 0 Interrupt Priority Level (BKPT_U0 IPL)—
Bits13–12
This field is used to set the interrupt priority levels for IRQs. This IRQ is limited to priorities 1 through 3.
It is disabled by default.
• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 1
• 10 = IRQ is priority level 2
• 11 = IRQ is priority level 3
5.6.1.3 EOnCE Step Counter Interrupt Priority Level (STPCNT IPL)—
Bits 11–10
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 1 through 3.
$11 IRQP0
R
PENDING [16:2] 1
W
$12 IRQP1
R
PENDING [32:17]
W
$13 IRQP2
R
PENDING [48:33]
W
$14 IRQP3
R
PENDING [64:49]
W
$15 IRQP4
R
PENDING [80:65]
W
$16 IRQP5
R
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
PEND-
ING
[81]
W
Reserved
$1D ICTL
R
INT IPIC VAB
INT_DIS
1
IRQB
STATE
IRQA
STATE
IRQB
EDG
IRQA
EDG
W
= Reserved
Base + $0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read
0 0
BKPT_U0 IPL STPCNT IPL
0 0 0 0 0 0 0 0 0 0
Write
RESET
0 0 0 0 0 0 0000000000
Add.
Offset
Register
Name
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Figure 5-2 ITCN Register Map Summary