Datasheet

56F8346 Technical Data, Rev. 15
110 Freescale Semiconductor
Preliminary
• Enforcing Flash security
These are discussed in more detail in the sections that follow.
6.2 Features
The SIM has the following features:
• Flash security feature prevents unauthorized access to code/data contained in on-chip Flash memory
• Power-saving clock gating for peripheral
• Three power modes (Run, Wait, Stop) to control power utilization
— Stop mode shuts down the 56800E core, system clock, peripheral clock, and PLL operation
— Stop mode entry can optionally disable PLL and Oscillator (low power vs. fast restart); must be
explicitly done
— Wait mode shuts down the 56800E core and unnecessary system clock operation
— Run mode supports full part operation
• Controls to enable/disable the 56800E core WAIT and STOP instructions
• Calculates base delay for reset extension based upon POR or RESET operations. Reset delay will be either
3 x 32 clocks (phased release of reset) for reset, except for POR, which is 2
21
clock cycles.
• Controls reset sequencing after reset
• Software-initiated reset
• Four 16-bit registers reset only by a Power-On Reset usable for general-purpose software control
• System Control Register
• Registers for software access to the JTAG ID of the chip