Datasheet

56F8346 Technical Data, Rev. 15
Freescale Semiconductor 5
Preliminary
56F8346/56F8146 Block Diagram - 144 LQFP
Program Controller
and
Hardware Looping Unit
Data ALU
16 x 16 + 36 -> 36-Bit MAC
Three 16-bit Input Registers
Four 36-bit Accumulators
Address
Generation Unit
Bit
Manipulation
Unit
PLL
Clock
Generator
EXTAL
Interrupt
Controller
COP/
Watchdog
SCI1 or
GPIOD
4
External
Address Bus
Switch
External Bus
Interface Unit
2
CLKMODE
IRQA
IRQB
External Data
Bus Switch
PDB
PDB
XAB1
XAB2
XDB2
CDBR
SCI0 or
GPIOE
SPI0 or
GPIOE
IPBus Bridge (IPBB)
Integration
Module
System
P
O
R
O
S
C
Decoding
Peripherals
Peripheral
Device Selects
RW
Control
IPAB IPWDB IPRDB
2
System Bus
R/W Control
PAB
PAB
CDBW
CDBR
CDBW
Clock
resets
JTAG/
EOnCE
Port
Digital Reg
Analog Reg
Low Voltage
Supervisor
V
CAP
V
DD
V
SS
V
DDA
V
SSA
5
47 52
V
PP
2
OCR_DIS
RESET
EXTBOOT
EMI_MODE
RSTO
4
3
6
PWM Outputs
Fault Inputs
PWMA
Current Sense Inputs
or GPIOC
3
4
6
PWM Outputs
Fault Inputs
PWMB
Current Sense Inputs
or GPIOD
3
Quad
Timer D or
GPIOE
Quad
Timer C or
GPIOE
AD0
AD1
ADCA
2
5
Quadrature
Decoder 0 or
Quad
Timer A or
GPIOC
FlexCAN
2
4
AD0
AD1
4
4
4
Temp_Sense
Quadrature
Decoder 1 or
Quad
Timer B or
SPI1 or
GPIOC
4
CLKO
Bus Control
6
2
8
7
9
2
XTAL
DS (CS1) or GPIOD9
PS (CS0) or GPIOD8
GPIOD0-1 or CS2-3
RD
WR
D7-15 or GPIOF0-8
D0-6 or GPIOF9-15
GPIOB0 or A16
A8-15 or GPIOA0-7
A0-5 or GPIOA8-13
A6-7 or GPIOE2-3
VREF
ADCB
16-Bit
56800E Core
Data Memory
4K x 16 Flash
8K x 16 RAM
Memory
Program Memory
64K x 16 Flash
2K x 16 RAM
4K x 16 Boot
Flash
Control
56F8346/56F8146 General Description
Note: Features in italics are NOT available in the 56F8146 device.
• Up to 60 MIPS at 60MHz core frequency
• DSP and MCU functionality in a unified,
C-efficient architecture
• Access up to 1MB of off-chip program and data memory
• Chip Select Logic for glueless interface to ROM and
SRAM
• 128KB of Program Flash
• 4KB of Program RAM
• 8KB of Data Flash
• 8KB of Data RAM
• 8KB of Boot Flash
• Up to two 6-channel PWM Modules
• Four 4-channel, 12-bit ADCs
• Temperature Sensor
• Up to two Quadrature Decoders
• Optional On-Chip Regulator
• FlexCAN module
• Two Serial Communication Interfaces (SCIs)
• Up to two Serial Peripheral Interfaces (SPIs)
• Up to four general-purpose Quad Timers
• Computer Operating Properly (COP) / Watchdog
• JTAG/Enhanced On-Chip Emulation (OnCE™) for
unobtrusive, real-time debugging
• Up to 62 GPIO lines
• 144-pin LQFP Package