56F8355/56F8155 Data Sheet Preliminary Technical Data 56F8300 16-Bit Digital Signal Controllers MC56F8355 Rev. 17 08/2009 freescale.
Document Revision History Version History Description of Change Rev 0.0 Initial release Rev 1.0 Fixed typos in Section 1.1.3; Replace any reference to Flash Interface Unit with Flash Memory Module; added note to Vcap pin in Table 2-2; corrected Table 4-4, removed unneccessary notes in Table 10-12; corrected temperature range in Table 10-14; added ADC calibration information to Table 10-23 and new graphs in Figure 10-22 Rev 2.0 Corrected 2.2μF to 0.1 μF low ESR capacitor in Table 2-2.
Document Revision History (Continued) Version History Rev 13 Description of Change • Table 2-2 — TDO pullup is not enabled • Table 2-2 — PWM pullup is not enabled • Table 2-2 — CAN_TX — remove pullup related text • Table 2-2 — Adding pullup is enabled to several rows for clarification • Section 4 — Factory Programmed Memory — add ADC callibration vector Rev 14 • Section 4 — Factory Programmed Memory — remove ADC callibration vector • Section 10 — Add Figure 10-1 • Section 10 — ADC correction factor refin
56F8355/56F8155 General Description Note: Features in italics are NOT available in the 56F8155 device.
Table of Contents Part 1 Overview . . . . . . . . . . . . . . . . . . . . . 6 1.1 1.2 1.3 1.4 1.5 1.6 56F8355/56F8155 Features . . . . . . . . . . . 6 Device Description . . . . . . . . . . . . . . . . . . 8 Award-Winning Development Environment . . . . . . . . . . . . . . . . . . 10 Architecture Block Diagram . . . . . . . . . . 10 Product Documentation . . . . . . . . . . . . . 14 Data Sheet Conventions. . . . . . . . . . . . . 15 Part 2 Signal/Connection Descriptions. 16 2.1 2.2 Introduction . . . . .
Part 1 Overview 1.1 56F8355/56F8155 Features 1.1.1 • • • • • • • • • • • • • • 1.1.
56F8355/56F8155 Features • • • Harvard architecture permits as many as three simultaneous accesses to program and data memory Flash security protection feature On-chip memory, including a low-cost, high-volume Flash solution — 256KB of Program Flash — 4KB of Program RAM — 8KB of Data Flash — 16KB of Data RAM — 16KB of Boot Flash • 1.1.4 EEPROM emulation capability Peripheral Circuits Note: Features in italics are NOT available in the 56F8155 device.
— In the 56F8355, four dedicated general-purpose Quad Timers totaling six dedicated pins: Timer C with two pins and Timer D with four pins — In the 56F8155, two Quad Timers; Timer A and Timer C both work in conjunction with GPIO • • • • • • • • • • • • 1.1.5 • • • • • • Optional On-Chip Regulator FlexCAN (CAN Version 2.
Device Description The 56F8355 and 56F8155 support program execution from internal memories. Two data operands can be accessed from the on-chip data RAM per instruction cycle. These devices also provide two external dedicated interrupt lines and up to 49 General Purpose Input/Output (GPIO) lines, depending on peripheral configuration. 1.2.
erase size is 1KB. The Boot Flash page erase size is 512 bytes; Boot Flash memory can also be either bulk or page erased. A key application-specific feature of the 56F8155 is the inclusion of one Pulse Width Modulator (PWM) module. This module incorporates three complementary, individually programmable PWM signal output pairs and can also support six independent PWM functions to enhance motor control functionality.
Architecture Block Diagram on-board regulator and power and ground signals. They also do not show the multiplexing between peripherals or the dedicated GPIOs. Please see Part 2, Signal/Connection Descriptions, to see which signals are multiplexed with those of other peripherals. Also shown in Figure 1-2 are connections between the PWM, Timer C and ADC blocks. These connections allow the PWM and/or Timer C to control the timing of the start of ADC conversions.
5 JTAG / EOnCE Boot Flash pdb_m[15:0] pab[20:0] Program Flash cdbw[31:0] Program RAM 56800E EMI* CHIP TAP Controller TAP Linking Module External JTAG Port xab1[23:0] xab2[23:0] 11 Address 4 Data 6 Control Data RAM Data Flash cdbr_m[31:0] xdb2_m[15:0] IPBus Bridge Flash NOT available on the 56F8155 device.
Architecture Block Diagram To/From IPBus Bridge Interrupt Controller CLKGEN (OSC/PLL) Low-Voltage Interrupt Timer A POR & LVI 4 System POR Quadrature Decoder 0 RESET SIM 4 Timer D COP Reset Timer B 4 COP 2 FlexCAN Quadrature Decoder 1 SPI 1 13 PWMA SYNC Output GPIO A 13 PWMB GPIO B SYNC Output GPIO C ch3i ch2i 2 Timer C GPIO D ch2o ch3o GPIO E GPIO F 4 2 SPI 0 8 ADCA SCI 0 TEMP_SENSE 2 8 ADCB 1 SCI 1 IPBus NOT available on the 56F8155 device.
Table 1-2 Bus Signal Names Name Function Program Memory Interface pdb_m[15:0] Program data bus for instruction word fetches or read operations. cdbw[15:0] Primary core data bus used for program memory writes. (Only these 16 bits of the cdbw[31:0] bus are used for writes to program memory.) pab[20:0] Program memory address bus. Data is returned on pdb_m bus. Primary Data Memory Interface Bus cdbr_m[31:0] Primary core data bus for memory reads. Addressed via xab1 bus.
Data Sheet Conventions Table 1-3 Chip Documentation Topic Description Order Number 56F8355/56F8155 Technical Data Sheet Electrical and timing specifications, pin descriptions, and package descriptions (this document) MC56F8355 Errata Details any chip issues that might be present MC56F8355E MC56F8155E 1.6 Data Sheet Conventions This data sheet uses the following conventions: OVERBAR This is used to indicate a signal that is active when pulled low. For example, the RESET pin is active when low.
Part 2 Signal/Connection Descriptions 2.1 Introduction The input and output signals of the 56F8355 and 56F8155 are organized into functional groups, as shown in Table 2-1 and as illustrated in Figure 2-1. In Table 2-2, each table row describes the signal or signals present on a pin.
Introduction Power VDD_IO Power Power VDDA_ADC VDDA_OSC_PLL Ground VSS Ground VSSA_ADC OCR_DIS VCAP1 - VCAP4 Other Supply Ports VPP1 & VPP2 CLKMODE EXTAL XTAL CLKO PLL and Clock *External Address Bus or GPIO *External Data Bus A8 - A13 (GPIOA0 - 5) GPIOB0-4 (A16 - 20) D7 - D10 (GPIOF0 - 3) 7 1 1 1 1 1 5 1 GPIOD0 - 5(CS2 - 7) 56F8355 1 4 2 1 1 1 1 1 1 1 1 1 1 6 1 6 5 3 4 4 6 3 SCI1 or GPIO TXD1 (GPIOD6) RXD1 (GPIOD7) JTAG/ EOnCE Port TCK TMS TDI TDO TRST 1 1 1 1 1 1 1 1
VDD_IO Power VDDA_ADC Power Power VDDA_OSC_PLL Ground VSS Ground VSSA_ADC OCR_DIS Other Supply Ports VCAP1 - VCAP4 VPP1 & VPP2 CLKMODE PLL and Clock *External Address Bus or GPIO *External Data Bus EXTAL XTAL CLKO A8 - A13 (GPIOA0 - 5) GPIOB0-4 (A16 - 20) D7 - D10 (GPIOF0 - 3) 7 1 1 1 1 1 5 1 GPIOD0 - 5(CS2 - 7) TXD0 (GPIOE0) RXD0 (GPIOE1) SCI1 or GPIO TXD1 (GPIOD6) RXD1 (GPIOD7) JTAG/ EOnCE Port TCK TMS TDI TDO TRST SPI0 OR GPIO 56F8155 1 4 2 1 1 1 1 SS0 (GPIOE7) 1 1 1 1 1
Signal Pins 2.2 Signal Pins After reset, all pins are by default the primary function. Any alternate functionality must be programmed. EMI is not functional in this package; since only part of the address/data bus is bonded out, use as GPIO pins. Note: Signals in italics are NOT available in the 56F8155 device. If the “State During Reset” lists more than one state for a pin, the first state is the actual reset state.
Table 2-2 Signal and Package Information for the 128-Pin LQFP (Continued) Signal Name Pin No. Type VSSA_ADC 95 Supply OCR_DIS 71 Input State During Reset Signal Description ADC Analog Ground — This pin supplies an analog ground to the ADC modules. Input On-Chip Regulator Disable — Tie this pin to VSS to enable the on-chip regulator. Tie this pin to VDD to disable the on-chip regulator. This pin is intended to be a static DC signal from power-up to shut down.
Signal Pins Table 2-2 Signal and Package Information for the 128-Pin LQFP (Continued) Signal Name Pin No. Type CLKO 6 Output State During Reset In reset, output is disabled Signal Description Clock Output — This pin outputs a buffered clock signal. Using the SIM CLKO Select Register (SIM_CLKOSR), this pin can be programmed as any of the following: disabled, CLK_MSTR (system clock), IPBus clock, oscillator output, prescaler clock and postscaler clock.
Table 2-2 Signal and Package Information for the 128-Pin LQFP (Continued) Signal Name Pin No. Type State During Reset GPIOB4 31 Schmitt Input/ Output Input, pullup enabled Signal Description Port B GPIO — This GPIO pin can be individually programmed as an input or output pin. (A20) Output Address Bus — A20 specifies one of the address lines for external program or data memory accesses.
Signal Pins Table 2-2 Signal and Package Information for the 128-Pin LQFP (Continued) Signal Name Pin No. Type GPIOD0 42 Input/ Output State During Reset Input, pullup enabled Output (CS2) GPIOD1 (CS3) 43 GPIOD2 (CS4) 44 GPIOD3 (CS5) 45 GPIOD4 (CS6) 46 GPIOD5 (CS7) 47 TXD0 7 Signal Description Port D GPIO — These six GPIO pins can be individually programmed as input or output pins.
Table 2-2 Signal and Package Information for the 128-Pin LQFP (Continued) Signal Name Pin No. Type RXD1 41 Input (GPIOD7) Input/ Output State During Reset Input, pullup enabled Signal Description Receive Data — SCI1 receive data input Port D GPIO — This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is SCI input. To deactivate the internal pullup resistor, clear bit 7 in the GPIOD_PUR register.
Signal Pins Table 2-2 Signal and Package Information for the 128-Pin LQFP (Continued) Signal Name Pin No. Type TRST 114 Schmitt Input State During Reset Input, pulled high internally Signal Description Test Reset — As an input, a low signal on this pin provides a reset signal to the JTAG TAP controller. To ensure complete hardware reset, TRST should be asserted whenever RESET is asserted.
Table 2-2 Signal and Package Information for the 128-Pin LQFP (Continued) Signal Name Pin No. Type INDEX0 1 Schmitt Input State During Reset Input, pullup enabled Signal Description Index — Quadrature Decoder 0, INDEX input (TA2) Schmitt Input/ Output TA2 — Timer A, Channel 2 (GPOPC6) Schmitt Input/ Output Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is INDEX0.
Signal Pins Table 2-2 Signal and Package Information for the 128-Pin LQFP (Continued) Signal Name Pin No. Type MOSI0 126 Input/ Output (GPIOE5) State During Reset In reset, output is disabled, pullup is enabled Input/ Output Signal Description SPI 0 Master Out/Slave In — This serial data pin is an output from a master device and an input to a slave device. The master device places data on the MOSI line a half-cycle before the clock edge the slave device uses to latch the data.
Table 2-2 Signal and Package Information for the 128-Pin LQFP (Continued) Signal Name Pin No. Type PHASEA1 9 Schmitt Input State During Reset Input, pullup enabled Signal Description Phase A1 — Quadrature Decoder 1, PHASEA input for decoder 1. (TB0) Schmitt Input/ Output TB0 — Timer B, Channel 0 (SCLK1) Schmitt Input/ Output SPI 1 Serial Clock — In the master mode, this pin serves as an output, clocking slaved listeners. In slave mode, this pin serves as the data clock input.
Signal Pins Table 2-2 Signal and Package Information for the 128-Pin LQFP (Continued) Signal Name Pin No. Type INDEX1 11 Schmitt Input State During Reset Input, pullup enabled Signal Description Index1 — Quadrature Decoder 1, INDEX input (TB2) Schmitt Input/ Output TB2 — Timer B, Channel 2 (MISO1) Schmitt Input/ Output SPI 1 Master In/Slave Out — This serial data pin is an input to a master device and output from a slave device.
Table 2-2 Signal and Package Information for the 128-Pin LQFP (Continued) State During Reset Signal Name Pin No. Type PWMA0 58 Output PWMA0 - 5 — These are six PWMA outputs. PWMA1 60 In reset, output is disabled PWMA2 61 PWMA3 63 PWMA4 64 PWMA5 66 ISA0 104 Schmitt Input Input, pullup enabled ISA0 - 2 — These three input current status pins are used for top/bottom pulse width correction in complementary channel operation for PWMA.
Signal Pins Table 2-2 Signal and Package Information for the 128-Pin LQFP (Continued) Signal Name Pin No.
Table 2-2 Signal and Package Information for the 128-Pin LQFP (Continued) State During Reset Signal Name Pin No.
Signal Pins Table 2-2 Signal and Package Information for the 128-Pin LQFP (Continued) Signal Name Pin No. Type State During Reset TD0 107 Schmitt Input/ Output Input, pullup enabled (GPIOE10) TD1 (GPIOE11) 108 TD2 (GPIOE12) 109 TD3 (GPIOE13) 110 IRQA 52 IRQB 53 Schmitt Input/ Output Signal Description TD0 - TD3 — Timer D, Channels 0, 1, 2 and 3 Port E GPIO — These GPIO pins can be individually programmed as input or output pins. At reset, these pins default to Timer functionality.
Table 2-2 Signal and Package Information for the 128-Pin LQFP (Continued) Signal Name Pin No. Type EXTBOOT Internal Ground Schmitt Input State During Reset Input, pullup enabled Signal Description External Boot — This input is tied to VDD to force the device to boot from off-chip memory (assuming that the on-chip Flash memory is not in a secure state). Otherwise, it is tied to ground. For details, see Table 4-4.
Introduction Part 3 On-Chip Clock Synthesis (OCCS) 3.1 Introduction Refer to the OCCS chapter of the 56F8300 Peripheral User Manual for a full description of the OCCS. The material contained here identifies the specific features of the OCCS design. Figure 3-1 shows the specific OCCS block diagram to reference from the OCCS chapter of the 56F8300 Peripheral User Manual.
The crystal and associated components should be mounted as near as possible to the EXTAL and XTAL pins to minimize output distortion and start up stabilization time.
Registers 3.2.3 External Clock Source The recommended method of connecting an external clock is illustrated in Figure 3-4. The external clock source is connected to XTAL and the EXTAL pin is grounded. Set OCCS_COHL bit high when using an external clock source as well. XTAL EXTAL External Clock VSS Note: When using an external clocking source with this configuration, the input “CLKMODE” should be high and the COHL bit in the OSCTL register should be set to 1.
4.2 Program Map The Program memory map is located in Table 4-4. The operating mode control bits (MA and MB) in the Operating Mode Register (OMR) control the Program memory map. At reset, these bits are set as indicated in Table 4-2. EXT_BOOT = EMI_MODE = 0 and cannot be changed in the 56F8355 or 56F8155.
Program Map Table 4-3 Changing OMR MA Value During Normal Operation OMR MA Chip Operating Mode 0 Use internal P-space memory map configuration 11 Use external P-space memory map configuration – If MB = 0 at reset, changing this bit has no effect. 1. Setting this bit can cause unpredictable results and is not recommended, since the EMI is not functional in this package. Table 4-4 shows the memory map options of the device.
5. Not accessible in reset configuration, since the address is above P:$00 FFFF. The higher bit address/GPIO (and/or chip selects) pins must be reconfigured before this external memory is accessible. 6. Not accessible in this part, since the EMI is not fully pinned out in this package; information in shaded areas not applicable to 56F8355/56F8155. 7. Two independent program flash blocks allow one to be programmed/erased while executing from another. Each block must have its own mass erase. 4.
Interrupt Vector Table Table 4-5 Interrupt Vector Table Contents1 (Continued) Vector Number Priority Level Vector Base Address + core 10 1-3 P:$14 OnCE Transmit Register Empty core 11 1-3 P:$16 OnCE Receive Register Full Peripheral Interrupt Function Reserved core 14 2 P:$1C SW Interrupt 2 core 15 1 P:$1E SW Interrupt 1 core 16 0 P:$20 SW Interrupt 0 core 17 0-2 P:$22 IRQA core 18 0-2 P:$24 IRQB Reserved LVI 20 0-2 P:$28 Low Voltage Detector (power sense) PLL 2
Table 4-5 Interrupt Vector Table Contents1 (Continued) Vector Number Priority Level Vector Base Address + DEC1 48 0-2 P:$60 Quadrature Decoder #1 INDEX Pulse DEC0 49 0-2 P:$62 Quadrature Decoder #0 Home Switch or Watchdog DEC0 50 0-2 P:$64 Quadrature Decoder #0 INDEX Pulse Peripheral Interrupt Function Reserved TMRD 52 0-2 P:$68 Timer D, Channel 0 TMRD 53 0-2 P:$6A Timer D, Channel 1 TMRD 54 0-2 P:$6C Timer D, Channel 2 TMRD 55 0-2 P:$6E Timer D, Channel 3 TMRC 56 0
Data Map 2. 4.4 Data Map Note: Data Flash is NOT available on the 56F8155 device.
Program Memory BOOT_FLASH_START + $1FFF BOOT_FLASH_START = $02_0000 PROG_FLASH_START + $01_FFFF PROG_FLASH_START + $01_FFF7 PROG_FLASH_START + $01_FFF6 Data Memory FM_BASE + $14 16KB Boot Banked Registers FM_BASE + $00 Unbanked Registers FM_PROG_MEM_TOP = $01_FFFF Configure Field DATA_FLASH_START + $0FFF 128KB Program 8KB DATA_FLASH_START + $0000 BLOCK 1 Odd (2 Bytes) $01_0003 BLOCK 1 Even (2 Bytes) $01_0002 BLOCK 1 Odd (2 Bytes) $01_0001 BLOCK 1 Even (2 Bytes) $01_0000 PROG_FLASH_START + $01_0000
Peripheral Memory Mapped Registers Table 4-8 EOnCE Memory Map (Continued) Address X:$FF FF8A Register Acronym OESCR Register Name External Signal Control Register Reserved X:$FF FF8E OBCNTR Breakpoint Unit [0] Counter Reserved X:$FF FF90 OBMSK (32 bits) Breakpoint 1 Unit [0] Mask Register X:$FF FF91 — Breakpoint 1 Unit [0] Mask Register X:$FF FF92 OBAR2 (32 bits) Breakpoint 2 Unit [0] Address Register X:$FF FF93 — Breakpoint 2 Unit [0] Address Register X:$FF FF94 OBAR1 (24 bits) Breakpo
Peripherals are listed in order of the base address. The following tables list all of the peripheral registers required to control or access the peripherals. Note: Features in italics are NOT available in the 56F8155 device.
Peripheral Memory Mapped Registers Table 4-10 External Memory Integration Registers Address Map (EMI_BASE = $00 F020) Address Offset Register Description Reset Values CSBAR 0 $0 Chip Select Base Address Register 0 0 x 0004 = 64K since EXTBOOT = EMI_MODE = 0 CSBAR 1 $1 Chip Select Base Address Register 1 0 x 0004 = 64K since EMI_MODE = 0 CSBAR 2 $2 Chip Select Base Address Register 2 CSBAR 3 $3 Chip Select Base Address Register 3 CSBAR 4 $4 Chip Select Base Address Register 4 CSBAR 5 $5
Table 4-11 Quad Timer A Registers Address Map (Continued) (TMRA_BASE = $00 F040) Register Acronym Address Offset Register Description TMRA0_CMP2 $1 Compare Register 2 TMRA0_CAP $2 Capture Register TMRA0_LOAD $3 Load Register TMRA0_HOLD $4 Hold Register TMRA0_CNTR $5 Counter Register TMRA0_CTRL $6 Control Register TMRA0_SCR $7 Status and Control Register TMRA0_CMPLD1 $8 Comparator Load Register 1 TMRA0_CMPLD2 $9 Comparator Load Register 2 TMRA0_COMSCR $A Comparator Status and
Peripheral Memory Mapped Registers Table 4-11 Quad Timer A Registers Address Map (Continued) (TMRA_BASE = $00 F040) Register Acronym Address Offset Register Description TMRA2_CNTR $25 Counter Register TMRA2_CTRL $26 Control Register TMRA2_SCR $27 Status and Control Register TMRA2_CMPLD1 $28 Comparator Load Register 1 TMRA2_CMPLD2 $29 Comparator Load Register 2 TMRA2_COMSCR $2A Comparator Status and Control Register Reserved TMRA3_CMP1 $30 Compare Register 1 TMRA3_CMP2 $31 Compare
Table 4-12 Quad Timer B Registers Address Map (Continued) (TMRB_BASE = $00 F080) Quad Timer B is NOT available in the 56F8155 device Register Acronym Address Offset Register Description TMRB0_CMPLD2 $9 Comparator Load Register 2 TMRB0_COMSCR $A Comparator Status and Control Register Reserved TMRB1_CMP1 $10 Compare Register 1 TMRB1_CMP2 $11 Compare Register 2 TMRB1_CAP $12 Capture Register TMRB1_LOAD $13 Load Register TMRB1_HOLD $14 Hold Register TMRB1_CNTR $15 Counter Register TMR
Peripheral Memory Mapped Registers Table 4-12 Quad Timer B Registers Address Map (Continued) (TMRB_BASE = $00 F080) Quad Timer B is NOT available in the 56F8155 device Register Acronym Address Offset Register Description TMRB3_CNTR $35 Counter Register TMRB3_CTRL $36 Control Register TMRB3_SCR $37 Status and Control Register TMRB3_CMPLD1 $38 Comparator Load Register 1 TMRB3_CMPLD2 $39 Comparator Load Register 2 TMRB3_COMSCR $3A Comparator Status and Control Register Table 4-13 Quad Tim
Table 4-13 Quad Timer C Registers Address Map (Continued) (TMRC_BASE = $00 F0C0) Register Acronym TMRC1_COMSCR Address Offset $1A Register Description Comparator Status and Control Register Reserved TMRC2_CMP1 $20 Compare Register 1 TMRC2_CMP2 $21 Compare Register 2 TMRC2_CAP $22 Capture Register TMRC2_LOAD $23 Load Register TMRC2_HOLD $24 Hold Register TMRC2_CNTR $25 Counter Register TMRC2_CTRL $26 Control Register TMRC2_SCR $27 Status and Control Register TMRC2_CMPLD1 $28 Comp
Peripheral Memory Mapped Registers Table 4-14 Quad Timer D Registers Address Map (Continued) (TMRD_BASE = $00 F100) Quad Timer D is NOT available in the 56F8155 device Register Acronym Address Offset Register Description TMRD0_LOAD $3 Load Register TMRD0_HOLD $4 Hold Register TMRD0_CNTR $5 Counter Register TMRD0_CTRL $6 Control Register TMRD0_SCR $7 Status and Control Register TMRD0_CMPLD1 $8 Comparator Load Register 1 TMRD0_CMPLD2 $9 Comparator Load Register 2 TMRD0_COMSCR $A Com
Table 4-14 Quad Timer D Registers Address Map (Continued) (TMRD_BASE = $00 F100) Quad Timer D is NOT available in the 56F8155 device Register Acronym Address Offset Register Description TMRD2_CMPLD2 $29 Comparator Load Register 2 TMRD2_COMSCR $2A Comparator Status and Control Register Reserved TMRD3_CMP1 $30 Compare Register 1 TMRD3_CMP2 $31 Compare Register 2 TMRD3_CAP $32 Capture Register TMRD3_LOAD $33 Load Register TMRD3_HOLD $34 Hold Register TMRD3_CNTR $35 Counter Register T
Peripheral Memory Mapped Registers Table 4-15 Pulse Width Modulator A Registers Address Map (Continued) (PWMA_BASE = $00 F140) PWMA is NOT available in the 56F8155 device Register Acronym Address Offset Register Description PWMA_PMDEADTM $C Dead Time Register PWMA_PMDISMAP1 $D Disable Mapping Register 1 PWMA_PMDISMAP2 $E Disable Mapping Register 2 PWMA_PMCFG $F Configure Register PWMA_PMCCR $10 Channel Control Register PWMA_PMPORT $11 Port Register PWMA_PMICCR $12 PWM Internal Correc
Table 4-17 Quadrature Decoder 0 Registers Address Map (DEC0_BASE = $00 F180) Register Acronym Address Offset Register Description DEC0_DECCR $0 Decoder Control Register DEC0_FIR $1 Filter Interval Register DEC0_WTR $2 Watchdog Timeout Register DEC0_POSD $3 Position Difference Counter Register DEC0_POSDH $4 Position Difference Counter Hold Register DEC0_REV $5 Revolution Counter Register DEC0_REVH $6 Revolution Hold Register DEC0_UPOS $7 Upper Position Counter Register DEC0_LPOS $
Peripheral Memory Mapped Registers Table 4-18 Quadrature Decoder 1 Registers Address Map (Continued) (DEC1_BASE = $00 F190) Quadrature Decoder 1 is NOT available in the 56F8155 device Register Acronym Address Offset Register Description DEC1_LIR $C Lower Initialization Register DEC1_IMR $D Input Monitor Register Table 4-19 Interrupt Control Registers Address Map (ITCN_BASE = $00 F1A0) Register Acronym Address Offset Register Description IPR 0 $0 Interrupt Priority Register 0 IPR 1 $1 Inter
Table 4-20 Analog-to-Digital Converter Registers Address Map (ADCA_BASE = $00 F200) Register Acronym Address Offset Register Description ADCA_CR 1 $0 Control Register 1 ADCA_CR 2 $1 Control Register 2 ADCA_ZCC $2 Zero Crossing Control Register ADCA_LST 1 $3 Channel List Register 1 ADCA_LST 2 $4 Channel List Register 2 ADCA_SDIS $5 Sample Disable Register ADCA_STAT $6 Status Register ADCA_LSTAT $7 Limit Status Register ADCA_ZCSTAT $8 Zero Crossing Status Register ADCA_RSLT 0 $9
Peripheral Memory Mapped Registers Table 4-20 Analog-to-Digital Converter Registers Address Map (Continued) (ADCA_BASE = $00 F200) Register Acronym Address Offset Register Description ADCA_HLMT 1 $1A High Limit Register 1 ADCA_HLMT 2 $1B High Limit Register 2 ADCA_HLMT 3 $1C High Limit Register 3 ADCA_HLMT 4 $1D High Limit Register 4 ADCA_HLMT 5 $1E High Limit Register 5 ADCA_HLMT 6 $1F High Limit Register 6 ADCA_HLMT 7 $20 High Limit Register 7 ADCA_OFS 0 $21 Offset Register 0 A
Table 4-21 Analog-to-Digital Converter Registers Address Map (Continued) (ADCB_BASE = $00 F240) Register Acronym Address Offset Register Description ADCB_RSLT 2 $B Result Register 2 ADCB_RSLT 3 $C Result Register 3 ADCB_RSLT 4 $D Result Register 4 ADCB_RSLT 5 $E Result Register 5 ADCB_RSLT 6 $F Result Register 6 ADCB_RSLT 7 $10 Result Register 7 ADCB_LLMT 0 $11 Low Limit Register 0 ADCB_LLMT 1 $12 Low Limit Register 1 ADCB_LLMT 2 $13 Low Limit Register 2 ADCB_LLMT 3 $14 Low L
Peripheral Memory Mapped Registers Table 4-22 Temperature Sensor Register Address Map (TSENSOR_BASE = $00 F270) Temperature Sensor is NOT available in the 56F8155 device Register Acronym TSENSOR_CNTL Address Offset $0 Register Description Control Register Table 4-23 Serial Communication Interface 0 Registers Address Map (SCI0_BASE = $00 F280) Register Acronym Address Offset Register Description SCI0_SCIBR $0 Baud Rate Register SCI0_SCICR $1 Control Register Reserved SCI0_SCISR $3 Status Regis
Table 4-26 Serial Peripheral Interface 1 Registers Address Map (SPI1_BASE = $00 F2B0) Register Acronym Address Offset Register Description SPI1_SPSCR $0 Status and Control Register SPI1_SPDSR $1 Data Size Register SPI1_SPDRR $2 Data Receive Register SPI1_SPDTR $3 Data Transmitter Register Table 4-27 Computer Operating Properly Registers Address Map (COP_BASE = $00 F2C0) Register Acronym Address Offset Register Description COPCTL $0 Control Register COPTO $1 Time Out Register COPCTR
Peripheral Memory Mapped Registers Table 4-29 GPIOA Registers Address Map (GPIOA_BASE = $00 F2E0) Register Acronym Address Offset Register Description Reset Value GPIOA_PUR $0 Pullup Enable Register 0 x 3FFF GPIOA_DR $1 Data Register 0 x 0000 GPIOA_DDR $2 Data Direction Register 0 x 0000 GPIOA_PER $3 Peripheral Enable Register 0 x 3FFF GPIOA_IAR $4 Interrupt Assert Register 0 x 0000 GPIOA_IENR $5 Interrupt Enable Register 0 x 0000 GPIOA_IPOLR $6 Interrupt Polarity Register 0
Table 4-31 GPIOC Registers Address Map (GPIOC_BASE = $00 F310) Register Acronym Address Offset Register Description Reset Value GPIOC_PUR $0 Pullup Enable Register 0 x 07FF GPIOC_DR $1 Data Register 0 x 0000 GPIOC_DDR $2 Data Direction Register 0 x 0000 GPIOC_PER $3 Peripheral Enable Register 0 x 07FF GPIOC_IAR $4 Interrupt Assert Register 0 x 0000 GPIOC_IENR $5 Interrupt Enable Register 0 x 0000 GPIOC_IPOLR $6 Interrupt Polarity Register 0 x 0000 GPIOC_IPR $7 Interrupt Pen
Peripheral Memory Mapped Registers Table 4-33 GPIOE Registers Address Map (GPIOE_BASE = $00 F330) Register Acronym Address Offset Register Description Reset Value GPIOE_PUR $0 Pullup Enable Register 0 x 3FFF GPIOE_DR $1 Data Register 0 x 0000 GPIOE_DDR $2 Data Direction Register 0 x 0000 GPIOE_PER $3 Peripheral Enable Register 0 x 3FFF GPIOE_IAR $4 Interrupt Assert Register 0 x 0000 GPIOE_IENR $5 Interrupt Enable Register 0 x 0000 GPIOE_IPOLR $6 Interrupt Polarity Register 0
Table 4-35 System Integration Module Registers Address Map (SIM_BASE = $00 F350) Register Acronym Address Offset Register Description SIM_CONTROL $0 Control Register SIM_RSTSTS $1 Reset Status Register SIM_SCR0 $2 Software Control Register 0 SIM_SCR1 $3 Software Control Register 1 SIM_SCR2 $4 Software Control Register 2 SIM_SCR3 $5 Software Control Register 3 SIM_MSH_ID $6 Most Significant Half JTAG ID SIM_LSH_ID $7 Least Significant Half JTAG ID SIM_PUDR $8 Pullup Disable Regis
Peripheral Memory Mapped Registers Table 4-37 Flash Module Registers Address Map (Continued) (FM_BASE = $00 F400) Register Acronym Address Offset Register Description Reserved Reserved FMPROT $10 Protection Register (Banked) FMPROTB $11 Protection Boot Register (Banked) Reserved FMUSTAT $13 User Status Register (Banked) FMCMD $14 Command Register (Banked) Reserved Reserved FMOPT 0 $1A 16-Bit Information Option Register 0 Hot temperature ADC reading of Temperature Sensor; value set during f
Table 4-38 FlexCAN Registers Address Map (Continued) (FC_BASE = $00 F800) FlexCAN is NOT available in the 56F8155 device Register Acronym FCRX15MASK_L Address Offset $D Register Description Receive Buffer 15 Mask Low Register Reserved FCSTATUS $10 Error and Status Register FCIMASK1 $11 Interrupt Masks 1 Register FCIFLAG1 $12 Interrupt Flags 1 Register FCR/T_ERROR_CNTRS $13 Receive and Transmit Error Counters Register Reserved Reserved Reserved FCMB0_CONTROL $40 Message Buffer 0 Control / St
Peripheral Memory Mapped Registers Table 4-38 FlexCAN Registers Address Map (Continued) (FC_BASE = $00 F800) FlexCAN is NOT available in the 56F8155 device Register Acronym FCMB2_DATA Address Offset $56 Register Description Message Buffer 2 Data Register Reserved FCMB3_CONTROL $58 Message Buffer 3 Control / Status Register FCMB3_ID_HIGH $59 Message Buffer 3 ID High Register FCMB3_ID_LOW $5A Message Buffer 3 ID Low Register FCMB3_DATA $5B Message Buffer 3 Data Register FCMB3_DATA $5C Messag
Table 4-38 FlexCAN Registers Address Map (Continued) (FC_BASE = $00 F800) FlexCAN is NOT available in the 56F8155 device Register Acronym Address Offset Register Description Reserved FCMB7_CONTROL $78 Message Buffer 7 Control / Status Register FCMB7_ID_HIGH $79 Message Buffer 7 ID High Register FCMB7_ID_LOW $7A Message Buffer 7 ID Low Register FCMB7_DATA $7B Message Buffer 7 Data Register FCMB7_DATA $7C Message Buffer 7 Data Register FCMB7_DATA $7D Message Buffer 7 Data Register FCMB7_D
Peripheral Memory Mapped Registers Table 4-38 FlexCAN Registers Address Map (Continued) (FC_BASE = $00 F800) FlexCAN is NOT available in the 56F8155 device Register Acronym FCMB10_DATA Address Offset $96 Register Description Message Buffer 10 Data Register Reserved FCMB11_CONTROL $98 Message Buffer 11 Control / Status Register FCMB11_ID_HIGH $99 Message Buffer 11 ID High Register FCMB11_ID_LOW $9A Message Buffer 11 ID Low Register FCMB11_DATA $9B Message Buffer 11 Data Register FCMB11_DATA
Table 4-38 FlexCAN Registers Address Map (Continued) (FC_BASE = $00 F800) FlexCAN is NOT available in the 56F8155 device Register Acronym Address Offset Register Description FCMB14_DATA $B5 Message Buffer 14 Data Register FCMB14_DATA $B6 Message Buffer 14 Data Register Reserved FCMB15_CONTROL $B8 Message Buffer 15 Control / Status Register FCMB15_ID_HIGH $B9 Message Buffer 15 ID High Register FCMB15_ID_LOW $BA Message Buffer 15 ID Low Register FCMB15_DATA $BB Message Buffer 15 Data Regis
Features 5.2 Features The ITCN module design includes these distinctive features: • • • • Programmable priority levels for each IRQ Two programmable Fast Interrupts Notification to SIM module to restart clocks out of Wait and Stop modes Drives initial address on the address bus after reset For further information, see Table 4-5, Interrupt Vector Table Contents. 5.3 Functional Description The Interrupt Controller is a slave on the IPBus.
Table 5-2 Interrupt Priority Encoding IPIC_LEVEL[1:0]1 01 Current Interrupt Priority Level Priority 0 Required Nested Exception Priority Priorities 1, 2, 3 10 Priority 1 Priorities 2, 3 11 Priorities 2 or 3 Priority 3 1. See IPIC field definition in Part 5.6.30.2 5.3.3 Fast Interrupt Handling Fast interrupts are described in the DSP56800E Reference Manual. The interrupt controller recognizes fast interrupts before the core does. A fast interrupt is defined (to the ITCN) by: 1.
Block Diagram 5.4 Block Diagram any0 Priority Level INT1 Level 0 82 -> 7 Priority Encoder 2 -> 4 Decode 7 INT VAB CONTROL any3 Level 3 IACK SR[9:8] Priority Level INT82 IPIC 82 -> 7 Priority Encoder 7 PIC_EN 2 -> 4 Decode Figure 5-1 Interrupt Controller Block Diagram 5.5 Operating Modes The ITCN module design contains two major modes of operation: • Functional Mode The ITCN is in this mode by default.
5.6 Register Descriptions A register address is the sum of a base address and an address offset. The base address is defined at the system level and the address offset is defined at the module level. The ITCN peripheral has 24 registers. Table 5-3 ITCN Register Summary (ITCN_BASE = $00F1A0) Register Acronym Base Address + Register Name Section Location IPR0 $0 Interrupt Priority Register 0 5.6.1 IPR1 $1 Interrupt Priority Register 1 5.6.2 IPR2 $2 Interrupt Priority Register 2 5.6.
Register Descriptions Table 5-3 ITCN Register Summary (ITCN_BASE = $00F1A0) (Continued) Register Acronym Add.
Add. Register Offset Name $14 IRQP3 $15 IRQP4 $16 IRQP5 15 14 13 12 11 10 9 8 R W R 7 6 5 4 3 2 1 0 1 1 1 1 1 1 PENDING [81] 1 IRQB STATE IRQA STATE IRQB EDG IRQA EDG PENDING [64:49] PENDING [80:65] W R 1 1 1 1 1 1 1 1 1 W Reserved $1D R ICTL INT IPIC VAB INT_DIS W = Reserved Figure 5-2 ITCN Register Map Summary 5.6.
Register Descriptions It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 1 10 = IRQ is priority level 2 11 = IRQ is priority level 3 5.6.1.4 Reserved—Bits 9–0 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 5.6.
• 11 = IRQ is priority level 3 5.6.2.4 EOnCE Trace Buffer Interrupt Priority Level (TRBUF IPL)— Bits 1–0 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 1 through 3. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 1 10 = IRQ is priority level 2 11 = IRQ is priority level 3 5.6.
Register Descriptions 5.6.3.3 Flash Memory Error Interrupt Priority Level (FMERR IPL)—Bits 11–10 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.3.4 PLL Loss of Lock Interrupt Priority Level (LOCK IPL)—Bits 9–8 This field is used to set the interrupt priority level for IRQs.
• • 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.3.8 External IRQ A Interrupt Priority Level (IRQA IPL)—Bits 1–0 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.
Register Descriptions • • • 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.4.4 FlexCAN Message Buffer Interrupt Priority Level (FCMSGBUF IPL)—Bits 9–8 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.4.
• 11 = IRQ is priority level 2 5.6.4.8 Reserved—Bits 1–0 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 5.6.5 Interrupt Priority Register 4 (IPR4) Base + $4 Read 15 14 SPI0_RCV IPL Write RESET 0 0 13 12 SPI1_XMIT IPL 0 0 11 10 9 8 7 6 SPI1_RCV IPL 0 0 0 0 0 0 0 5 4 GPIOA IPL 0 0 0 0 0 3 2 GPIOB IPL 0 0 1 0 GPIOC IPL 0 0 Figure 5-7 Interrupt Priority Register 4 (IPR4) 5.6.5.
Register Descriptions 5.6.5.4 Reserved—Bits 9–6 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 5.6.5.5 GPIOA Interrupt Priority Level (GPIOA IPL)—Bits 5–4 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.5.
5.6.6.1 Quadrature Decoder 1 INDEX Pulse Interrupt Priority Level (DEC1_XIRQ IPL)—Bits 15–14 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.6.
Register Descriptions 5.6.6.5 Reserved—Bits 7–6 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 5.6.6.6 SCI1 Transmitter Idle Interrupt Priority Level (SCI1_TIDL IPL)— Bits 5–4 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.6.
5.6.7.1 Timer C, Channel 0 Interrupt Priority Level (TMRC0 IPL)— Bits 15–14 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.7.2 Timer D, Channel 3 Interrupt Priority Level (TMRD3 IPL)— Bits 13–12 This field is used to set the interrupt priority level for IRQs.
Register Descriptions 5.6.7.5 Timer D, Channel 0 Interrupt Priority Level (TMRD0 IPL)— Bits 7–6 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.7.6 Reserved—Bits 5–4 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 5.6.7.
5.6.8.1 Timer A, Channel 0 Interrupt Priority Level (TMRA0 IPL)— Bits 15–14 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.8.2 Timer B, Channel 3 Interrupt Priority Level (TMRB3 IPL)— Bits 13–12 This field is used to set the interrupt priority level for IRQs.
Register Descriptions 5.6.8.5 Timer B, Channel 0 Interrupt Priority Level (TMRB0 IPL)—Bits 7–6 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.8.6 Timer C, Channel 3 Interrupt Priority Level (TMRC3 IPL)—Bits 5–4 This field is used to set the interrupt priority level for IRQs.
5.6.9.1 SCI0 Receiver Full Interrupt Priority Level (SCI0_RCV IPL)— Bits 15–14 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.9.2 SCI0 Receiver Error Interrupt Priority Level (SCI0_RERR IPL)— Bits 13–12 This field is used to set the interrupt priority level for IRQs.
Register Descriptions 5.6.9.6 Timer A, Channel 3 Interrupt Priority Level (TMRA3 IPL)—Bits 5–4 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.9.7 Timer A, Channel 2 Interrupt Priority Level (TMRA2 IPL)—Bits 3–2 This field is used to set the interrupt priority level for IRQs.
• • • 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.10.2 PWM B Fault Interrupt Priority Level (PWMB_F IPL)—Bits 13–12 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.10.
Register Descriptions 5.6.10.6 ADC B Zero Crossing or Limit Error Interrupt Priority Level (ADCB_ZC IPL)—Bits 5–4 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.10.
5.6.11.2 Interrupt Vector Base Address (VECTOR BASE ADDRESS)— Bits 12–0 The contents of this register determine the location of the Vector Address Table. The value in this register is used as the upper 13 bits of the interrupt Vector Address Bus (VAB[20:0]). The lower eight bits are determined based upon the highest-priority interrupt. They are then appended onto VBA before presenting the full interrupt address to the 56800E core; see Part 5.3.1 for details. 5.6.
Register Descriptions 5.6.14 Fast Interrupt 0 Vector Address High Register (FIVAH0) Base + $D 15 14 13 12 11 10 9 8 7 6 5 Read 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 2 1 0 FAST INTERRUPT 0 VECTOR ADDRESS HIGH Write RESET 3 0 0 0 0 0 Figure 5-16 Fast Interrupt 0 Vector Address High Register (FIVAH0) 5.6.14.1 Reserved—Bits 15–5 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 5.6.14.
5.6.16 Fast Interrupt 1 Vector Address Low Register (FIVAL1) Base + $F 15 14 13 12 11 10 Read 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 FAST INTERRUPT 1 VECTOR ADDRESS LOW Write RESET 0 0 0 0 0 0 0 0 0 0 Figure 5-18 Fast Interrupt 1 Vector Address Low Register (FIVAL1) 5.6.16.1 Fast Interrupt 1 Vector Address Low (FIVAL1)—Bits 15–0 The lower 16 bits of vector address are used for Fast Interrupt 1.
Register Descriptions 5.6.18.2 Reserved—Bit 0 This bit is reserved or not implemented. It is read as 1 and cannot be modified by writing. 5.6.19 IRQ Pending 1 Register (IRQP1) $Base + $12 15 14 13 12 11 10 9 Read 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 PENDING [32:17] Write RESET 1 1 1 1 1 1 1 1 1 Figure 5-21 IRQ Pending 1 Register (IRQP1) 5.6.19.
5.6.21 IRQ Pending 3 Register (IRQP3) Base + $14 15 14 13 12 11 10 9 Read 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 PENDING [64:49] Write RESET 1 1 1 1 1 1 1 1 1 Figure 5-23 IRQ Pending 3 Register (IRQP3) 5.6.21.1 IRQ Pending (PENDING)—Bits 64–49 This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2 through 81. • • 0 = IRQ pending for this vector number 1 = No IRQ pending for this vector number 5.6.
Register Descriptions 5.6.23.2 IRQ Pending (PENDING)—Bit 81 This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2 through 81. • • 0 = IRQ pending for this vector number 1 = No IRQ pending for this vector number 5.6.24 Reserved—Base + 17 5.6.25 Reserved—Base + 18 5.6.26 Reserved—Base + 19 5.6.27 Reserved—Base + 1A 5.6.28 Reserved—Base + 1B 5.6.29 Reserved—Base + 1C 5.6.
• 11 = Required nested exception priority level is 3 5.6.30.3 Vector Number - Vector Address Bus (VAB)—Bits 12–6 This read-only field shows the vector number (VAB[7:1]) used at the time the last IRQ was taken. This field is only updated when the 56800E core jumps to a new interrupt service routine. Note: Nested interrupts may cause this field to be updated before the original interrupt service routine can read it. 5.6.30.
Resets 5.7.2 ITCN After Reset After reset, all of the ITCN registers are in their default states. This means all interrupts are disabled except the core IRQs with fixed priorities: • • • • • • • • Illegal Instruction SW Interrupt 3 HW Stack Overflow Misaligned Long Word Access SW Interrupt 2 SW Interrupt 1 SW Interrupt 0 SW Interrupt LP These interrupts are enabled at their fixed priority levels. 56F8355 Technical Data, Rev.
Part 6 System Integration Module (SIM) 6.1 Overview The SIM module is a system catchall for the glue logic that ties together the system-on-chip. It controls distribution of resets and clocks and provides a number of control features.
Operating Mode Register • Reset Mode, which has two submodes: — POR and RESET operation The 56800E core and all peripherals are reset. This occurs when the internal POR is asserted or the RESET pin is asserted. — COP reset and software reset operation The 56800E core and all peripherals are reset. The MA bit within the OMR is not changed. This allows the software to determine the boot mode (internal or external boot) to be used on the next reset.
6.
Register Descriptions Add.
6.5.1 SIM Control Register (SIM_CONTROL) Base + $0 15 14 13 12 11 10 9 8 7 6 5 4 Read 0 0 0 0 0 0 0 0 0 0 ONCE EBL SW RST 0 0 0 0 0 0 0 0 0 0 0 0 Write RESET 3 2 1 0 STOP_ DISABLE WAIT_ DISABLE 0 0 0 0 Figure 6-3 SIM Control Register (SIM_CONTROL) 6.5.1.1 Reserved—Bits 15–6 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 6.5.1.
Register Descriptions Base + $1 15 14 13 12 11 10 9 8 7 6 Read 0 0 O 0 0 0 0 0 0 0 5 SWR 4 COPR 3 EXTR 2 1 0 0 0 0 0 POR Write RESET 0 0 0 0 0 0 0 0 0 0 Figure 6-4 SIM Reset Status Register (SIM_RSTSTS) 6.5.2.1 Reserved—Bits 15–6 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 6.5.2.
Base + $2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 Read FIELD Write RESET 0 0 0 0 0 0 0 0 Figure 6-5 SIM Software Control Register 0 (SIM_SCR0) 6.5.3.1 Software Control Data 1 (FIELD)—Bits 15–0 This register is reset only by the Power-On Reset (POR). It has no part-specific functionality and is intended for use by a software developer to contain data that will be unaffected by the other reset sources (RESET pin, software reset, and COP reset). 6.5.
Register Descriptions Table 2-2 to identify which pins can deactivate the internal pullup resistor. Base + $8 15 Read 0 Write RESET 0 14 13 12 11 10 9 8 7 6 5 0 PWMA1 CAN EMI_ MODE RESET IRQ XBOOT 0 0 0 0 0 0 PWMB PWMA0 0 0 4 CTRL 0 3 0 0 2 1 0 0 0 0 0 0 0 JTAG 0 0 Figure 6-8 SIM Pullup Disable Register (SIM_PUDR) 6.5.6.1 Reserved—Bit 15 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 6.5.6.
6.5.6.10 Reserved—Bit 6 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 6.5.6.11 CTRL—Bit 5 This bit controls the pullup resistors on the WR and RD pins. 6.5.6.12 Reserved—Bit 4 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 6.5.6.13 JTAG—Bit 3 This bit controls the pullup resistors on the TRST, TMS and TDI pins. 6.5.6.14 Reserved—Bit 2–0 This bit field is reserved or not implemented.
Register Descriptions • 1 = Peripheral output function of GPIOB7 is defined to be the oscillator clock (MSTR_OSC, see Figure 3-4) 6.5.7.3 • • 0 = Peripheral output function of GPIOB6 is defined to be A22 1 = Peripheral output function of GPIOB6 is defined to be SYS_CLK2 6.5.7.4 • • Alternate GPIOB Peripheral Function for A20 (A20)—Bit 6 0 = Peripheral output function of GPIOB4 is defined to be A20 1 = Peripheral output function of GPIOB4 is defined to be the prescaler clock 6.5.7.
6.5.8 GPIO Peripheral Select Register (SIM_GPS) The GPIO Peripheral Select register can be used to multiplex out any one of the three alternate peripherals for GPIOC. The default peripheral is Quad Decoder 1 and Quad Decoder 1, (NOT available in the 56F8155 device); these peripherals work together. The four I/O pins associated with GPIOC can function as GPIO, Quad Decoder 1/Quad Decoder 1, or as SPI 1 signals.
Register Descriptions Table 6-2 Control of Pads Using SIM_GPS Control 1 (Continued) GPIOC_PER GPIOC_DTR SIM_GPS Quad Timer SCR Register OEN bits Control Registers SPI input 1 — 1 — SPI output 1 — 1 — Pin Function Comments See SPI controls for determining the direction of each of the SPI pins. 1. This applies to the four pins that serve as Quad Decoder / Quad Timer / SPI / GPIOC functions. A separate set of control bits is used for each pin. 2. Reset configuration 3.
6.5.8.5 GPIOC0 (C0)—Bit 0 This bit selects the alternate function for GPIOC0. • • 0 = PHASEA1/TB0 (default) 1 = SCLK1 6.5.9 Peripheral Clock Enable Register (SIM_PCE) The Peripheral Clock Enable register is used enable or disable clocks to the peripherals as a power savings feature. The clocks can be individually controlled for each peripheral on the chip.
Register Descriptions • 0 = The clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.6 Decoder 0 Enable (DEC0)—Bit 10 Each bit controls clocks to the indicated peripheral. • • 1 = Clocks are enabled 0 = The clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.7 Quad Timer D Enable (TMRD)—Bit 9 Each bit controls clocks to the indicated peripheral. • • 1 = Clocks are enabled 0 = The clock is not provided to the peripheral (the peripheral is disabled) 6.5.
6.5.9.13 Serial Peripheral Interface 1 Enable (SPI1)—Bit 3 Each bit controls clocks to the indicated peripheral. • • 1 = Clocks are enabled 0 = The clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.14 Serial Peripheral Interface 0 Enable (SPI0)—Bit 2 Each bit controls clocks to the indicated peripheral. • • 1 = Clocks are enabled 0 = The clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.
Register Descriptions “Hard Coded” Address Portion Instruction Portion 6 Bits from I/O Short Address Mode Instruction 16 Bits from SIM_ISALL Register 2 Bits from SIM_ISALH Register Full 24-Bit for Short I/O Address Figure 6-13 I/O Short Address Determination With this register set, an interrupt driver can set the SIM_ISALL register pair to point to its peripheral registers and then use the I/O Short addressing mode to reference them.
Base + $E 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 Read ISAL[21:6] Write RESET 1 1 1 1 1 1 1 1 1 Figure 6-15 I/O Short Address Location Low Register (SIM_ISALL) 6.5.10.2 Input/Output Short Address Low (ISAL[21:6])—Bit 15–0 This field represents the lower 16 address bits of the “hard coded” I/O short address. 6.
Stop and Wait Mode Disable Function Table 6-3 Clock Operation in Power-Down Modes (Continued) Mode Stop Core Clocks Peripheral Clocks Description System clocks continue to be generated in the SIM, but most are gated prior to reaching memory, core and peripherals. The only possible recoveries from Stop mode are: 1. CAN traffic (1st message will be lost) 2. Non-clocked interrupts 3. COP reset 4. External reset 5.
The 56800E core contains both STOP and WAIT instructions. Both put the CPU to sleep. For lowest power consumption in Stop mode, the PLL can be shut down. This must be done explicitly before entering Stop mode, since there is no automatic mechanism for this. When the PLL is shut down, the 56800E system clock must be set equal to the oscillator output. Some applications require the 56800E STOP and WAIT instructions to be disabled.
Flash Access Blocking Mechanisms of security. When Flash security mode is enabled in accordance with the method described in the Flash Memory module specification, the device will disable the core EOnCE debug capabilities. Normal program execution is otherwise unaffected. 7.2 Flash Access Blocking Mechanisms The 56F8355/56F8155 have several operating functional and test modes.
The value of the JTAG FM_CLKDIV[6:0] will replace the value of the FM register FMCLKD that divides down the system clock for timed events, as illustrated in Figure 7-1. FM_CLKDIV[6] will map to the PRDIV8 bit, and FM_CLKDIV[5:0] will map to the DIV[5:0] bits. The combination of PRDIV8 and DIV must divide the FM input clock down to a frequency of 150kHz-200kHz.
Introduction input clock 16MHz. Because that is greater than 12.8MHz, PRDIV8 = FM_CLKDIV[6] = 1. Using the following equation yields a DIV value of 9 for a clock of 200kHz, and a DIV value of 10 for a clock of 181kHz. This translates to an FM_CLKDIV[6:0] value of $49 or $4A, respectively.
in the 56F8300 Peripheral User Manual. 8.2 Memory Maps The width of the GPIO port defines how many bits are implemented in each of the GPIO registers. Based on this and the default function of each of the GPIO pins, the reset values of the GPIOx_PUR and GPIOx_PER registers will change from port to port. Tables 4-29 through 4-34 define the actual reset values of these registers for these devices. 8.3 Configuration There are six GPIO ports defined on the 56F8355/56F8155.
Configuration Table 8-1 56F8355 GPIO Ports Configuration GPIO Port Port Width Available Pins in 56F8355 D 13 11 2 pins - EMI CSn 4 pins - EMI CSn - Can only be used as GPIO 2 pins - SCI1 2 pins - EMI CSn - Not available in this package 3 pins - PWMB current sense EMI Chip Selects EMI Chip Selects SCI1 N/A PWMB current sense E 14 12 2 pins - SCI0 2 pins - EMI Address pins - Not available in this package 4 pins - SPI0 2 pins - TMRC 4 pins - TMRD SCI0 N/A SPI0 TMRC TMRD F 16 4 4 pins - EMI Dat
Table 8-3 GPIO External Signals Map Pins in shaded rows are not available in 56F8355 / 56F8155 Pins in italics are NOT available in the 56F8155 device GPIO Port GPIOA GPIOB GPIO Bit Reset Function Functional Signal Package Pin # 0 Peripheral A81 15 1 Peripheral A91 16 2 Peripheral A101 17 3 Peripheral A111 18 4 Peripheral A121 19 5 Peripheral A131 20 6 N/A 7 N/A 8 N/A 9 N/A 10 N/A 11 N/A 12 N/A 13 N/A 0 GPIO A161 27 1 GPIO A171 28 2 GPIO A181 29 3
Configuration Table 8-3 GPIO External Signals Map (Continued) Pins in shaded rows are not available in 56F8355 / 56F8155 Pins in italics are NOT available in the 56F8155 device GPIO Port GPIOC GPIOD GPIO Bit Reset Function Functional Signal Package Pin # 0 Peripheral PHASEA1 / TB0 / SCLK12 9 1 Peripheral PHASEB1 / TB1 / MOSI12 10 2 Peripheral INDEX1 / TB2 / MISO12 11 3 Peripheral HOME1 / TB3 / SS12 12 4 Peripheral PHASEA0 / TA0 127 5 Peripheral PHASEB0 / TA1 128 6 Peripheral
Table 8-3 GPIO External Signals Map (Continued) Pins in shaded rows are not available in 56F8355 / 56F8155 Pins in italics are NOT available in the 56F8155 device GPIO Port GPIO Bit Reset Function Functional Signal Package Pin # 0 Peripheral TXD0 7 1 Peripheral RXD0 8 2 N/A 3 N/A 4 Peripheral SCLK0 124 5 Peripheral MOSI0 126 6 Peripheral MISO0 125 7 Peripheral SS0 123 8 Peripheral TC0 111 9 Peripheral TC1 113 10 Peripheral TD0 107 11 Peripheral TD1 108 12 Pe
56F8355 Information 1. Not useful in reset configuration in this package - reconfigure as GPIO 2. See Part 6.5.8 to determine how to select peripherals from this set; DEC1 is the selected peripheral at reset Part 9 Joint Test Action Group (JTAG) 9.1 56F8355 Information Please contact your Freescale marketing device/package-specific BSDL information. representative or authorized distributor for Part 10 Specifications 10.
Table 10-1 Absolute Maximum Ratings (VSS = VSSA_ADC = 0) Characteristic Supply voltage ADC Supply Voltage Oscillator / PLL Supply Voltage Internal Logic Core Supply Voltage Symbol Notes VDD_IO VDDA_ADC, VREFH VREFH must be less than or equal to VDDA_ADC VDDA_OSC_PLL Min Max Unit - 0.3 4.0 V - 0.3 4.0 V - 0.3 4.0 V VDD_CORE OCR_DIS is High - 0.3 3.0 V Input Voltage (digital) VIN Pin Groups 1, 2, 5, 6, 9, 10 -0.3 6.0 V Input Voltage (analog) VINA Pin Groups 11, 12, 13 -0.3 4.
General Characteristics Table 10-2 56F8355/56F8155 ElectroStatic Discharge (ESD) Protection Characteristic Min Typ Max Unit ESD for Human Body Model (HBM) 2000 — — V ESD for Machine Model (MM) 200 — — V ESD for Charge Device Model (CDM) 500 — — V Table 10-3 Thermal Characteristics6 Value Characteristic Comments Symbol Unit Notes 128-pin LQFP Junction to ambient Natural convection Junction to ambient (@1m/sec) RθJA 50.8 °C/W 2 RθJMA 46.
TA = Ambient temperature Note: The 56F8155 device is guaranteed to 40MHz and specified to meet Industrial requirements only; CAN is NOT available on the 56F8155 device. Table 10-4 Recommended Operating Conditions (VREFLO = 0V, VSS = VSSA_ADC = 0V, VDDA = VDDA_ADC = VDDA_OSC_PLL ) Characteristic Supply voltage ADC Supply Voltage Oscillator / PLL Supply Voltage Symbol Notes VDD_IO VDDA_ADC, VREFH VREFH must be less VDD_CORE Device Clock Frequency FSYSCLK Typ Max Unit 3 3.3 3.6 V 3 3.3 3.
DC Electrical Characteristics 10.2 DC Electrical Characteristics Note: The 56F8155 device is specified to meet Industrial requirements only; CAN is NOT available on the 56F8155 device. Table 10-5 DC Electrical Characteristics At Recommended Operating Conditions; see Table 10-4 Characteristic Symbol Notes Min Typ Max Unit Test Conditions Output High Voltage VOH 2.4 — — V IOH = IOHmax Output Low Voltage VOL — — 0.4 V IOL = IOLmax IIH Pin Groups 1, 2, 5, 6, 9 — 0 +/- 2.
μA 0 –10 –30 –50 –70 –90 0 1 2 3 Volts Figure 10-1 Maximum Current — Schmitt Input DC Response –40 °C, 3.6 V Table 10-6 Power-On Reset Low Voltage Parameters Characteristic Symbol Min Typ Max Units POR Trip Point POR 1.75 1.8 1.9 V LVI, 2.5 volt Supply, trip point1 VEI2.5 — 2.14 — V LVI, 3.3 volt supply, trip point2 VEI3.3 — 2.7 — V Bias Current I bias — 110 130 μA 1. When VDD_CORE drops below VEI2.5, an interrupt is generated. 2. When VDD_CORE drops below VEI3.
DC Electrical Characteristics Table 10-7 Current Consumption per Power Supply Pin (Typical) On-Chip Regulator Enabled (OCR_DIS = Low) Mode IDD_IO1 IDD_ADC IDD_OSC_PLL 6mA 0uA 155uA Stop1 Test Conditions • 8MHz Device Clock • All peripheral clocks are off • ADC powered off • PLL powered off Stop2 5.1mA 0uA 145uA • External Clock is off • All peripheral clocks are off • ADC powered off • PLL powered off 1. No Output Switching 2.
Table 10-9. Regulator Parameters Characteristic Symbol Min Typical Max Unit Unloaded Output Voltage (0mA Load) VRNL 2.25 — 2.75 V Loaded Output Voltage (200mA load) VRL 2.25 — 2.75 V Line Regulation @ 250mA load (VDD33 ranges from 3.0V to 3.6V) VR 2.25 — 2.75 V Short Circuit Current (output shorted to ground) Iss — — 700 mA I bias — 5.
AC Electrical Characteristics Table 10-11 Temperature Sense Parametrics Characteristics Symbol Min Typical Max Unit Room Trim Temp. 1, 2 TRT 24 26 28 °C Hot Trim Temp. (Industrial)1,2 THT 122 125 128 °C Hot Trim Temp. (Automotive)1,2 THT 147 150 153 °C Output Voltage @ VDDA_ADC = 3.3V, TJ =0°C1 VTS0 — 1.370 — V VDDA_ADC 3.0 3.3 3.
• Data Valid state, when a signal level has reached VOL or VOH • Data Invalid state, when a signal level is in transition between VOL and VOH Data2 Valid Data1 Valid Data1 Data3 Valid Data2 Data3 Data Tri-stated Data Invalid State Data Active Data Active Figure 10-3 Signal States 10.
Phase Locked Loop Timing VIH External Clock 90% 50% 10% 90% 50% 10% tfall tPW tPW trise VIL Note: The midpoint is VIL + (VIH – VIL)/2. Figure 10-4 External Clock Timing 10.6 Phase Locked Loop Timing Table 10-14 PLL Timing Characteristic Symbol Min Typ Max Unit External reference crystal frequency for the PLL1 fosc 4 8 8.4 MHz PLL output frequency2 (fOUT) fop 160 — 260 MHz PLL stabilization time3 -40° to +125°C tplls — 1 10 ms 1.
Table 10-15 Crystal Oscillator Parameters Characteristic Symbol Min Typ Max Unit Bias Current, high-drive mode IBIASH — 250 290 μA Bias Current, low-drive mode IBIASL — 80 110 μA IPD — 0 1 μA Quiescent Current, power-down mode 10.
Reset, Stop, Wait, Mode Select, and Interrupt Timing IRQA, IRQB tIRW Figure 10-6 External Interrupt Timing (Negative-Edge-Sensitive) A0–A15 First Interrupt Instruction Execution tIDM IRQA, IRQB a) First Interrupt Instruction Execution General Purpose I/O Pin tIG IRQA, IRQB b) General Purpose I/O Figure 10-7 External Level-Sensitive Interrupt Timing IRQA, IRQB tIRI A0–A15 First Interrupt Vector Instruction Fetch Figure 10-8 Interrupt from Wait State Timing tIW IRQA tIF A0–A15 First Instruction F
10.9 Serial Peripheral Interface (SPI) Timing Table 10-17 SPI Timing1 Characteristic Symbol Cycle time Master Slave Min Max Unit 50 50 — — ns ns — 25 — — ns ns — 100 — — ns ns 17.6 25 — — ns ns 24.1 25 — — ns ns 20 0 — — ns ns 0 2 — — ns ns 4.8 15 ns 3.7 15.2 ns — — 4.5 20.4 ns ns 0 0 — — ns ns — — 11.5 10.0 ns ns — — 9.7 9.
Serial Peripheral Interface (SPI) Timing SS SS is held High on master (Input) tC tR tF tCL SCLK (CPOL = 0) (Output) tCH tF tR tCL SCLK (CPOL = 1) (Output) tDH tCH tDS MISO (Input) MSB in Bits 14–1 tDI MOSI (Output) Master MSB out tDV Bits 14–1 tF LSB in tDI(ref) Master LSB out tR Figure 10-10 SPI Master Timing (CPHA = 0) 56F8355 Technical Data, Rev.
SS (Input) SS is held High on master tC tF tR tCL SCLK (CPOL = 0) (Output) tCH tF tCL SCLK (CPOL = 1) (Output) tCH tDS tR MISO (Input) MSB in tDH Bits 14–1 tDI tDV(ref) MOSI (Output) LSB in tDI(ref) tDV Master MSB out Bits 14– 1 Master LSB out tF tR Figure 10-11 SPI Master Timing (CPHA = 1) SS (Input) tC tF tCL SCLK (CPOL = 0) (Input) tR tCH tELD tCL SCLK (CPOL = 1) (Input) tCH tA MISO (Output) Slave MSB out tDV tDH MSB in tF tR Bits 14–1 tDS MOSI (Input) tELG B
Quad Timer Timing SS (Input) tF tC tR tCL SCLK (CPOL = 0) (Input) tCH tELG tELD tCL SCLK (CPOL = 1) (Input) tDV tCH tR tA MISO (Output) tD tF Slave MSB out Bits 14–1 tDS tDV Slave LSB out tDI tDH MOSI (Input) MSB in Bits 14–1 LSB in Figure 10-13 SPI Slave Timing (CPHA = 1) 10.
Timer Inputs PIN PINHL PINHL POUT POUTHL POUTHL Timer Outputs Figure 10-14 Timer Timing 10.11 Quadrature Decoder Timing Table 10-19 Quadrature Decoder Timing1, 2 Characteristic Symbol Min Max Unit See Figure Quadrature input period PIN 4T + 12 — ns 10-15 Quadrature input high / low period PHL 2T + 6 — ns 10-15 Quadrature phase period PPH 1T + 3 — ns 10-15 1. In the formulas listed, T = the clock cycle. For 60MHz operation, T=16.67ns. 2.
Serial Communication Interface (SCI) Timing 10.12 Serial Communication Interface (SCI) Timing Table 10-20 SCI Timing1 Characteristic Symbol Min Max Unit See Figure BR — (fMAX/16) Mbps — RXD3 Pulse Width RXDPW 0.965/BR 1.04/BR ns 10-16 TXD4 Pulse Width TXDPW 0.965/BR 1.04/BR ns 10-17 Baud Rate2 1. Parameters listed are guaranteed by design. 2. fMAX is the frequency of operation of the system clock, ZCLK, in MHz, which is 60MHz for the 56F8355 device and 40MHz for the 56F8155 device.
CAN_RX CAN receive data pin (Input) T WAKEUP Figure 10-18 Bus Wake Up Detection 10.
Analog-to-Digital Converter (ADC) Parameters TCK (Input) tDS TDI TMS (Input) tDH Input Data Valid tDV TDO (Output) Output Data Valid tTS TDO (Output) tDV TDO (Output) Output Data Valid Figure 10-20 Test Access Port Timing Diagram TRST (Input) tTRST Figure 10-21 TRST Timing Diagram 10.
Table 10-23 ADC Parameters (Continued) Characteristic Symbol Min Typ Max Unit Conversion time tADC — 6 — tAIC cycles3 Sample time tADS — 1 — tAIC cycles3 Input capacitance CADI — 5 — pF Input injection current5, per pin IADI — — 3 mA Input injection current, total IADIT — — 20 mA VREFH current IVREFH — 1.
Analog-to-Digital Converter (ADC) Parameters Figure 10-22 ADC Absolute Error Over Processing and Temperature Extremes Before and After Calibration for VDCin = 0.60V and 2.70V Note: The absolute error data shown in the graphs above reflects the effects of both gain error and offset error.
10.16 Equivalent Circuit for ADC Inputs Figure 10-23 illustrates the ADC input circuit during sample and hold. S1 and S2 are always open/closed at the same time that S3 is closed/open. When S1/S2 are closed and S3 is open, one input of the sample and hold circuit moves to VREFH - VREFH / 2, while the other charges to the analog input voltage.
Power Consumption PLL, and voltage references. These sources operate independently of processor state or operating frequency. B, the internal [state-dependent component], reflects the supply current required by certain on-chip resources only when those resources are in use. These include RAM, Flash memory and the ADCs. C, the internal [dynamic component], is classic C*V2*F CMOS power dissipation corresponding to the 56800E core and standard cell logic.
Part 11 Packaging 11.1 56F8355 Package and Pin-Out Information PHASEB0 PHASEA0 MOSI0 MISO0 SCLK0 SS0 VCAP2 CAN_RX CAN_TX VPP1 TDO TDI TMS TCK TRST TC1 VDD_IO TC0 TD3 TD2 TD1 TD0 ISA2 ISA1 ISA0 ANB7 This section contains package and pin-out information for the 56F8355. This device comes in a 128-pin low-profile quad flat pack (LQFP).
56F8355 Package and Pin-Out Information Table 11-1 56F8355 128-Pin LQFP Package Identification by Pin Number Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name Pin No.
Table 11-1 56F8355 128-Pin LQFP Package Identification by Pin Number (Continued) Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name 29 GPIOB2 61 PWMA2 93 VREFH 125 MISO0 30 GPIOB3 62 VDD_IO 94 VDDA_ADC 126 MOSI0 31 GPIOB4 63 PWMA3 95 VSSA_ADC 127 PHASEA0 32 PWMB0 64 PWMA4 96 ANB0 128 PHASEB0 1. Primary function is not available in this package configuration; GPIO function must be used instead. 11.
PHASEB0 PHASEA0 MOSI0 MISO0 SCLK0 SS0 VCAP2 NC NC VPP1 TDO TDI TMS TCK TRST TC1 VDD_IO TC0 GPIOE13 GPIOE12 GPIOE11 GPIOE10 GPIOC10 GPIOC9 GPIOC8 ANB7 56F8155 Package and Pin-Out Information INDEX0 HOME0 VSS VDD_IO Orientation Mark 103 PIN 1 VPP2 CLKO TXD0 RXD0 SCLK1 MOSI1 MISO1 SS1 VCAP4 VDD_IO GPIOA0 GPIOA1 GPIOA2 GPIOA3 GPIOA4 GPIOA5 VSS GPIOF0 GPIOF1 GPIOF2 VDD_IO 65 39 PWMB5 TXD1 RXD1 GPIOD0 GPIOD1 GPIOD2 GPIOD3 GPIOD4 GPIOD5 ISB0 VCAP1 ISB1 ISB2 IRQA IRQB FAULTB0 FAULTB1 FAULTB2 FAULTB3 NC VSS
Table 11-2 56F8155 128-Pin LQFP Package Identification by Pin Number (Continued) Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name Pin No.
56F8155 Package and Pin-Out Information Table 11-2 56F8155 128-Pin LQFP Package Identification by Pin Number (Continued) Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name 32 PWMB0 64 NC 96 ANB0 128 PHASEB0 1. Primary function is not available in this package configuration; GPIO function must be used instead. 56F8355 Technical Data, Rev.
DIM NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE H IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS A, B, AND D TO BE DETERMINED AT DATUM PLANE H. 5. DIMENSIONS D AND E TO BE DETERMINED AT SEATING PLANE C. 6. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 PER SIDE.
Thermal Design Considerations Please see www.freescale.com for the most current case outline. Part 12 Design Considerations 12.
ΨJT = Thermal characterization parameter (oC)/W PD = Power dissipation in package (W) The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and over about 1mm of wire extending from the junction.
Power Distribution and I/O Ring Implementation • • • Bypass the VDD and VSS layers of the PCB with approximately 100μF, preferably with a high-grade capacitor such as a tantalum capacitor Because the device’s output signals have fast rise and fall times, PCB trace lengths should be minimal Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance.
Part 13 Ordering Information Table 13-1 lists the pertinent information needed to place an order. Consult a Freescale Semiconductor sales office or authorized distributor to determine availability and to order parts. Table 13-1 Ordering Information Part Supply Voltage Package Type Pin Count Frequency (MHz) MC56F8355 3.0–3.6 V Low-Profile Quad Flat Pack (LQFP) 128 MC56F8355 3.0–3.6 V Low-Profile Quad Flat Pack (LQFP) MC56F8155 3.0–3.
Power Distribution and I/O Ring Implementation 56F8355 Technical Data, Rev.
56F8355 Technical Data, Rev.
Power Distribution and I/O Ring Implementation 56F8355 Technical Data, Rev.
56F8355 Technical Data, Rev.
Power Distribution and I/O Ring Implementation THIS PAGE IS INTENTIONALLY BLANK 56F8355 Technical Data, Rev.
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