Datasheet

56F8355 Technical Data, Rev. 17
104 Freescale Semiconductor
Preliminary
Part 6 System Integration Module (SIM)
6.1 Overview
The SIM module is a system catchall for the glue logic that ties together the system-on-chip. It controls
distribution of resets and clocks and provides a number of control features. The system integration module
is responsible for the following functions:
• Reset sequencing
• Clock generation & distribution
• Stop/Wait control
• Pullup enables for selected peripherals
• System status registers
• Registers for software access to the JTAG ID of the chip
• Enforcing Flash security
These are discussed in more detial in the sections that follow.
6.2 Features
The SIM has the following features:
• Flash security feature prevents unauthorized access to code/data contained in on-chip Flash memory
• Power-saving clock gating for peripheral
• Three power modes (Run, Wait, Stop) to control power utilization
— Stop mode shuts down the 56800E core, system clock, peripheral clock, and PLL operation
— Stop mode entry can optionally disable PLL and Oscillator (low power vs. fast restart); must be
explicitly done
— Wait mode shuts down 56800E core and unnecessary system clock operation
— Run mode supports full part operation
• Controls to enable/disable the 56800E core WAIT and STOP instructions
• Calculates base delay for reset extension based upon POR or RESET
operations. Reset delay will be 3 x 32
clocks (phased release of reset) for reset, except for POR, which is 2
21
clock cycles.
• Controls reset sequencing after reset
• Software-initiated reset
• Four 16-bit registers reset only by a Power-On Reset usable for general-purpose software control
• System Control Register
• Registers for software access to the JTAG ID of the chip
6.3 Operating Modes
Since the SIM is responsible for distributing clocks and resets across the chip, it must understand the
various chip operating modes and take appropriate action. These are: