Datasheet

56F8355 Technical Data, Rev. 17
108 Freescale Semiconductor
Preliminary
6.5.1 SIM Control Register (SIM_CONTROL)
Figure 6-3 SIM Control Register (SIM_CONTROL)
6.5.1.1 Reserved—Bits 15–6
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.5.1.2 OnCE Enable (OnCE EBL)—Bit 5
• 0 = OnCE clock to 56800E core enabled when core TAP is enabled
• 1 = OnCE clock to 56800E core is always enabled
6.5.1.3 Software Reset (SWRST)—Bit 4
This bit is always read as 0. Writing 1 to this field will cause the part to reset.
6.5.1.4 Stop Disable (STOP_DISABLE)—Bits 3–2
• 00 - STOP mode will be entered when the 56800E core executes a STOP instruction
• 01 - The 56800E STOP instruction will not cause entry into Stop mode; stop_disable can be reprogrammed
in the future
• 10 - The 56800E STOP instruction will not cause entry into Stop mode; stop_disable can then only be
changed by resetting the device
• 11 - Same operation as 10
6.5.1.5 Wait Disable (WAIT_DISABLE)—Bits 1–0
• 00 - WAIT mode will be entered when the 56800E core executes a WAIT instruction
• 01 - The 56800E WAIT instruction will not cause entry into Wait mode; wait_disable can be reprogrammed
in the future
• 10 - The HawkV2 WAIT instruction will not cause entry into Wait mode; wait_disable can then only be
changed by resetting the device
• 11 - Same operation as 10
6.5.2 SIM Reset Status Register (SIM_RSTSTS)
Bits in this register are set upon any system reset and are initialized only by a Power-On Reset (POR). A
reset (other than POR) will only set bits in the register; bits are not cleared. Only software should clear this
register.
Base + $0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read
0 0 0 0 0 0 0 0 0 0
ONCE
EBL
SW
RST
STOP_
DISABLE
WAIT_
DISABLE
Write
RESET
0000000000000000