Datasheet

56F8355 Technical Data, Rev. 17
120 Freescale Semiconductor
Preliminary
Figure 6-15 I/O Short Address Location Low Register (SIM_ISALL)
6.5.10.2 Input/Output Short Address Low (ISAL[21:6])—Bit 15–0
This field represents the lower 16 address bits of the “hard coded” I/O short address.
6.6 Clock Generation Overview
The SIM uses an internal master clock from the OCCS (CLKGEN) module to produce the peripheral and
system (core and memory) clocks. The maximum master clock frequency is 120MHz. Peripheral and
system clocks are generated at half the master clock frequency and therefore at a maximum 60MHz. The
SIM provides power modes (Stop, Wait) and clock enables (SIM_PCE register, CLK_DIS, ONCE_EBL)
to control which clocks are in operation. The OCCS, power modes, and clock enables provide a flexible
means to manage power consumption.
Power utilization can be minimized in several ways. In the OCCS, crystal oscillator, and PLL may be shut
down when not in use. When the PLL is in use, its prescaler and postscaler can be used to limit PLL and
master clock frequency. Power modes permit system and/or peripheral clocks to be disabled when unused.
Clock enables provide the means to disable individual clocks. Some peripherals provide further controls
to disable unused subfunctions. Refer to Part 3 On-Chip Clock Synthesis (OCCS), and the 56F8300
Peripheral User Manual for further details.
6.7 Power Down Modes Overview
The 56F8355/56F8155 operate in one of three power-down modes, as shown in Table 6-3.
Base + $E
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read
ISAL[21:6]
Write
RESET
1111111 11111 1 1 11
Table 6-3 Clock Operation in Power-Down Modes
Mode Core Clocks Peripheral Clocks Description
Run Active Active Device is fully functional
Wait Core and memory
clocks disabled
Active Peripherals are active and can produce interrupts if they
have not been masked off.
Interrupts will cause the core to come out of its
suspended state and resume normal operation.
Typically used for power-conscious applications.