Datasheet

Configuration
56F8355 Technical Data, Rev. 17
Freescale Semiconductor 129
Preliminary
GPIOC
0Peripheral
PHASEA1 / TB0 / SCLK1
2
9
1Peripheral
PHASEB1 / TB1 / MOSI1
2
10
2Peripheral
INDEX1 / TB2 / MISO1
2
11
3Peripheral
HOME1 / TB3 / SS1
2
12
4 Peripheral PHASEA0 / TA0 127
5 Peripheral PHASEB0 / TA1 128
6 Peripheral INDEX0 / TA2 1
7 Peripheral HOME0 / TA3 2
8Peripheral ISA0 104
9Peripheral ISA1 105
10 Peripheral ISA2 106
GPIOD
0GPIO
CS2
1
42
1GPIO
CS3
1
43
2GPIO
CS4
1
44
3GPIO
CS5
1
45
4GPIO
CS6
1
46
5GPIO
CS7
1
47
6Peripheral TXD1 40
7PeripheralRXD1 41
8
N/A
9 N/A
10 Peripheral ISB0 48
11 Peripheral ISB1 50
12 Peripheral ISB2 51
Table 8-3 GPIO External Signals Map (Continued)
Pins in shaded rows are not available in 56F8355 / 56F8155
Pins in italics are NOT available in the 56F8155 device
GPIO Port GPIO Bit
Reset Function
Functional Signal Package Pin #