Datasheet

Quad Timer Timing
56F8355 Technical Data, Rev. 17
Freescale Semiconductor 147
Preliminary
Figure 10-13 SPI Slave Timing (CPHA = 1)
10.10 Quad Timer Timing
Table 10-18 Timer Timing
1, 2
1. In the formulas listed, T = the clock cycle. For 60MHz operation, T = 16.67ns.
2. Parameters listed are guaranteed by design.
Characteristic Symbol Min Max Unit See Figure
Timer input period P
IN
2T + 6 — ns 10-14
Timer input high / low period P
INHL
1T + 3 — ns 10-14
Timer output period P
OUT
1T - 3 — ns 10-14
Timer output high / low period P
OUTHL
0.5T - 3 — ns 10-14
SCLK (CPOL = 0)
(Input)
SCLK (CPOL = 1)
(Input)
MISO
(Output)
MOSI
(Input)
Slave MSB out Bits 14–1
t
C
t
CL
t
CL
t
CH
t
DI
MSB in Bits 14–1 LSB in
SS
(Input)
t
CH
t
DH
t
F
t
R
Slave LSB out
t
D
t
A
t
ELD
t
DV
t
F
t
R
t
ELG
t
DV
t
DS