Datasheet

Signal Pins
56F8355 Technical Data, Rev. 17
Freescale Semiconductor 33
Preliminary
TD0
(GPIOE10)
107 Schmitt
Input/
Output
Schmitt
Input/
Output
Input,
pullup
enabled
TD0 - TD3 — Timer D, Channels 0, 1, 2 and 3
Port E GPIO — These GPIO pins can be individually programmed
as input or output pins.
At reset, these pins default to Timer functionality.
To deactivate the internal pullup resistor, clear the appropriate bit
of the GPIOE_PUR register. See Part 6.5.6 for details.
TD1
(GPIOE11)
108
TD2
(GPIOE12)
109
TD3
(GPIOE13)
110
IRQA
52 Schmitt
Input
Input,
pullup
enabled
External Interrupt Request A and B — The IRQA and IRQB
inputs are asynchronous external interrupt requests during Stop
and Wait mode operation. During other operating modes, they are
synchronized external interrupt requests, which indicate an
external device is requesting service. They can be programmed to
be level-sensitive or negative-edge triggered.
To deactivate the internal pullup resistor, set the IRQ bit in the
SIM_PUDR register. See Part 6.5.6 for details.
IRQB
53
RESET 78 Schmitt
Input
Input,
pullup
enabled
Reset — This input is a direct hardware reset on the processor.
When RESET is asserted low, the device is initialized and placed
in the reset state. A Schmitt trigger input is used for noise
immunity. The internal reset signal will be deasserted
synchronous with the internal clocks after a fixed number of
internal clocks.
To ensure complete hardware reset, RESET
and TRST should be
asserted together. The only exception occurs in a debugging
environment when a hardware device reset is required and the
JTAG/EOnCE module must not be reset. In this case, assert
RESET
but do not assert TRST.
Note: The internal Power-On Reset will assert on initial power-up.
To deactivate the internal pullup resistor, set the RESET
bit in the
SIM_PUDR register. See Part 6.5.6 for details.
RSTO
77 Output Output Reset Output — This output reflects the internal reset state of the
chip.
Table 2-2 Signal and Package Information for the 128-Pin LQFP (Continued)
Signal Name Pin No. Type
State
During
Reset
Signal Description