Datasheet

56F8355 Technical Data, Rev. 17
6 Freescale Semiconductor
Preliminary
Part 1 Overview
1.1 56F8355/56F8155 Features
1.1.1 Core
• Efficient 16-bit 56800E family controller engine with dual Harvard architecture
• Up to 60 Million Instructions Per Second (MIPS) at 60MHz core frequency
• Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC)
• Four 36-bit accumulators, including extension bits
• Arithmetic and logic multi-bit shifter
• Parallel instruction set with unique DSP addressing modes
• Hardware DO and REP loops
• Three internal address buses
• Four internal data buses
• Instruction set supports both DSP and controller functions
• Controller-style addressing modes and instructions for compact code
• Efficient C compiler and local variable support
• Software subroutine and interrupt stack with depth limited only by memory
• JTAG/EOnCE debug programming interface
1.1.2 Differences Between Devices
Table 1-1 outlines the key differences between the 56F8355 and 56F8155 devices.
1.1.3 Memory
Note: Features in italics are NOT available in the 56F8155 device.
Table 1-1 Device Differences
Feature 56F8355 56F8155
Guaranteed Speed 60MHz/60 MIPS 40MHz/40MIPS
Program RAM 4KB Not Available
Data Flash 8KB Not Available
PWM 2 x 6 1 x 6
CAN 1 Not Available
Quad Timer 4 2
Quadrature Decoder 2 x 4 1 x 4
Temperature Sensor 1 Not Available